United Microelectronics Corp.

National Cheng-Kung University

Zhi-Hsien Chen

Jar-Ferr Yang

Chyou-Hsiung Hwang

Shih-Chang Hisa

An apparatus for selecting the primary/secondary and the master/slave configuration of an enhanced IDE interface. The apparatus has a first and a second connector, each for connecting to a cascade of a first and a second IDE drive device. The apparatus comprises a primary/secondary configuration logic and a master/slave configuration logic. The primary/secondary configuration logic is utilized for selectively configuring the first and second connectors of the enhanced IDE interface as the primary and secondary connectors of the IDE interface respectively, or as the secondary and primary connectors of the enhanced IDE interface respectively. The master/slave configuration logic is utilized for selectively configuring the first and second IDE drive devices in each of the cascades as the master and slave drives respectively, or as the slave and master drives respectively.

Apparatus for flexibly selecting primary and secondary connectors and

A two-dimensional inverse discrete cosine transform (2-D IDCT) processor comprises cosine angle index generators, pipelined multipliers and a symmetrical kernel. The 2-D IDCT processor of the invention has a five-stage pipelined structure for carrying out a coefficient-by-coefficient 2-D IDCT algorithm and can be operated at a clock rate of more than 50 MHz to achieve a pixel rate of about 400 MHz.

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Hsinchu Hsien, Taiwan

Zhi-Hsien Chen