United Microelectronics Corp.

Zhi-Biao Zhou

Chi-Fa Ku

Shao-Hui Wu

Chen-Bin Lin

Su Xing

Tien-Yu Hsieh

Chun-Yuan Wu

Hai-Biao Yao

Wei-Jin Wang

A method for manufacturing a semiconductor module is provided. The method includes: providing a substrate, wherein the substrate comprises a front side and at least one semiconductor element formed on the front side; forming a shielding structure on the at least one semiconductor element; forming a piezoelectric layer on the shielding structure.

Method for manufacturing semiconductor module including piezoelectric layer

A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

Semiconductor device and method for fabricating semiconductor device

A semiconductor module and a method for manufacturing the same are provided. The semiconductor module includes a substrate comprising a front side and at least one semiconductor device formed on the front side, a shielding structure formed on the at least one semiconductor device, and a piezoelectric layer formed on the shielding structure.

Semiconductor module including piezoelectric layer and method for manufacturing the same

A semiconductor device is provided, including a buried oxide layer, having a first side and a second side. A silicon-based device layer is disposed on the first side of the buried oxide layer. The silicon-based device layer includes a first interconnection structure. A semiconductor-based device layer is disposed on the second side of the buried oxide layer. The semiconductor-based device layer includes a second interconnection structure.

Semiconductor device integrating silicon-based device with semiconductor-based device and method for fabricating the same

A method of manufacturing a memory structure including following steps is provided. Two gate stack structures are formed on a substrate. A conductive material layer is conformally formed on the two gate stack structures. The conductive material layer includes two protrusions located on the two gate stack structures. Hard mask spacers are formed on two sides of each of the two protrusions. A first etching process is performed to remove a portion of the conductive material layer by using the hard mask spacers as a mask. A second etching process is performed to completely remove the hard mask spacers. Then, a third etching process is performed on the conductive material layer to form a first conductive spacer and a second conductive spacer located on one side and the other side of the two gate stack structures and to form a conductive layer located between the two gate stack structures.

Method of manufacturing memory structure

A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

A semiconductor device integrated with memory device includes a substrate, having a first side and a second side. A transistor circuit layer is disposed over the substrate at the first side. An interconnect structure layer is disposed over the transistor circuit layer with electric connection to form a circuit route. A memory cell layer is disposed over the interconnect structure layer or over a second side of the substrate, in connection to the circuit route. The memory cell layer includes a plurality of memory cells, and a cell structure of the memory cells includes an oxide semiconductor field effect transistor and a memory element.

Semiconductor device integrated with memory device and fabrication method thereof

A semiconductor device is provided. The semiconductor device includes an insulating structure and a dielectric structure. The insulating structure is disposed on a substrate and has a plurality of openings. The dielectric structure is disposed on the insulating structure and extending into the plurality of openings.

Semiconductor device

A method for forming a semiconductor device includes: providing a structure having a first stop layer formed above a substrate, a first dielectric layer formed on the first stop layer, a second stop layer formed on the first dielectric layer, and conductive lines formed in the first dielectric layer and spaced apart from each other; forming a first dummy layer on the second stop layer; patterning the first dummy layer to form a first patterned dummy layer; forming a second dummy layer on the first dummy layer to form a first trench; etching back the second dummy layer and the first patterned dummy layer to form a second trench, wherein the second trench is self-aligned with the first trench. The second trench extends downwardly to the first dielectric layer and forms an opening at the second stop layer.

Method for forming semiconductor device and semiconductor device fabricated by the same

An integrated LED display is provided. The integrated LED display includes a complementary metal-oxide-semiconductor (CMOS) wafer including a driver circuitry fabricated on a substrate. Further, an insulating layer is disposed over the CMOS wafer. A conductive semiconductor layer is disposed on the insulating layer. A LED array is disposed on the conductive semiconductor layer and the LED array connected to the driver circuitry. The LED array includes a photo device array, disposed on the conductive semiconductor layer, and a switch device array, disposed on the conductive semiconductor layer.

Integrated LED display and fabrication method thereof

A semiconductor device and a method of fabricating the same are provide. The fabricating method includes providing a silicon-on-insulator (SOI) substrate that includes, from bottom to top, a substrate, a first insulating layer and a semiconductor layer. The semiconductor layer is patterned to form a plurality of dummy patterns. A second insulating layer is formed around the plurality of dummy patterns. The plurality of dummy patterns are removed to form a plurality of openings. A dielectric structure is formed on the substrate and fills into the plurality of openings.

Semiconductor device and method of fabricating the same

A method for fabricating handling wafer includes providing a substrate, having a front side and a back side. The front side of the substrate is disposed on a supporting pin. A first oxide layer is formed surrounding the substrate. A portion of the first oxide layer is removed to expose the front side of the substrate. An alignment mark is formed on the front side of the substrate.

Method for fabricating handling wafer

A semiconductor device and an integrated circuit are provided. The semiconductor device includes a field effect transistor, a negative capacitor and a control circuit, which are disposed at different horizontal levels on a substrate. The field effect transistor includes a front gate, a back gate and an oxide semiconductor layer disposed between the front gate and the back gate. The negative capacitor is electrically connected to the back gate of the field effect transistor. The negative capacitor includes a pair of electrodes and a ferroelectric material layer disposed between the pair of electrodes. The negative capacitor is electrically connected between the back gate of the field effect transistor and the control circuit, the control circuit is configured to charge the negative capacitor and to asses a voltage between the pair of electrodes of the negative capacitor.

Semiconductor device and integrated circuit

A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

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Singapore, Singapore

Zhi-Biao Zhou