Intel Corporation

Zhenyu Zhu

Mikal Hunsaker

Daniel Nemiroff

Anoop Mukker

Nobuyuki Suzuki

David W Vogel

Karthi R Vadivelu

Chai Huat Gan

Navtej Singh

Amit Kumar Srivastava

Mahesh S Natu

Michael T Klinglesmith

William A Stevens, Jr

Karunakara Kotary

Michael E Deisher

Malay Trivedi

Sivakumar Radhakrishnan

Shaun M Conrad

Asad Azam

Michael Berger

Satheesh Chellappan

Kenneth Foust

Srikanth Potluri

Nivedita Aggarwal

Mark T Feuerstraeter

Basavaraj B Astekar

Kar Leong Wong

Christopher J Lake

Piotr Michael Kwidzinski

Mazen G Gedeon

Rajesh Bhaskar

Sylvia Downing

Kie Woon Lim

Chris Ruffin

Darryl Adams

Randall L Albion

Rahul Bhatt

Joel L Finkel

Lean Kim Ong

Siow Hoay Lim

Aditya Bhutada

Computing platforms and related methods for providing accessible user interfaces are disclosed. An example apparatus includes a display controller to a display controller to sample a region of a display frame associated with a location of a touch on a display screen of a user device and logic circuitry to, after a Basic Input Output System (BIOS) is operational in the user device and prior to loading of an operating system of the user device, identify content in the display region and cause at least one output device to generate an output representative of the content, the output including at least one of an audible output or a haptic output.

Computing platforms and related methods for providing accessible user interfaces

An apparatus to facilitate descriptor resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store firmware for a computer system platform, wherein the firmware comprises a primary descriptor including access permission details for platform components and a secondary descriptor including a backup copy of the access permission details and a controller, coupled to the first non-volatile memory, including recovery hardware to detect a problem during a platform reset with the primary descriptor, recover the contents of the primary descriptor from the backup copy included in the secondary descriptor and store the contents of the backup copy to primary descriptor.

Firmware descriptor resiliency mechanism

An example includes detecting receiving a bus turn-around (BTA) sequence after detecting a voltage level; sending a BTA acknowledgement in response to the BTA sequence; and sending a configuration command to a peripheral device after the interface is initialized based on the BTA acknowledgement.

Method for interface initialization using bus turn-around

Described is an apparatus comprising a first interface, a second interface, a third interface, and an interconnection fabric. The first interface may transfer a first stream of data traffic. The second interface, which may be an enhanced Serial Peripheral Interface (eSPI) interface, may transfer a second stream of data traffic and a third stream of data traffic. The third interface may transfer a fourth stream of data traffic. The interconnection fabric may couple the first interface to the second interface and may couple the second interface to the third interface. The second interface may initiate a transfer of an outbound data stream from one of the second stream of data traffic or the third stream of data traffic based on an available-space credit indicator. The second interface may receive an inbound data stream based upon the outbound data stream.

Low power data processing offload using external platform component

Apparatuses and methods relating to an enhanced serial peripheral interface (eSPI) port expander circuitry are described. In an embodiment, an apparatus includes an upstream eSPI port, a plurality of downstream eSPI ports, and an eSPI aggregator. The upstream eSPI port is to operate as an eSPI slave on an upstream eSPI bus. Each of the plurality of downstream eSPI ports is to operate as an eSPI master on a corresponding one of a plurality of downstream eSPI buses. The eSPI aggregator is to forward or broadcast transactions from the upstream eSPI bus to one or more of the plurality of downstream eSPI buses and to aggregate responses from one or more of the downstream eSPI buses.

Enhanced serial peripheral interface (eSPI) port expander

Embodiments may include apparatus, systems, and methods associated with an Enhanced Serial Peripheral Interface (eSPI) channel interface to couple to a data bus to link an eSPI primary device to an eSPI secondary device. In embodiments, the eSPI primary device includes an eSPI device controller and is coupled to the channel interface and transmits a notification of a crash event, e.g., a catastrophic error (CATERR), via packet-based signaling, such as a virtual wire (VW) over the data bus to allow the eSPI primary device to transmit the notification of the crash event without allocation of a dedicated wire signal for the notification between the eSPI primary device and the eSPI secondary device. Other embodiments may be described and/or claimed.

Enhanced serial peripheral interface (eSPI) signaling for crash event notification

Embodiments include a serial bus controller that may be coupled to an in band serial peripheral interface (SPI) link, to request a write of data and a subsequent read of the data from a memory device and in response to the request to read the data, receive a bit error report and optionally correct the bit error over the in band SPI link. Embodiments include a memory device, e.g., a flash memory device, to detect and report the bit error over the in band SPI link, where the flash memory device, in response to a request to write and/or erase data, calculates or determines an error correction code (ECC) and stores corresponding parity data. In embodiments, after receiving a subsequent request to read the data, the flash memory device accesses the stored parity data to check the ECC for a bit error and if a bit error is detected, reports the detected bit error over the in band SPI link. Other embodiments may be described and claimed.

Apparatus, systems, and methods to detect and/or correct bit errors using an in band link over a serial peripheral interface

In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

System, apparatus and method for sharing a flash device among multiple masters of a computing platform

Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.

Tunneling functional safety communications over an enhanced serial peripheral interface

An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

Platform environment control interface tunneling via enhanced serial peripheral interface

An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.

A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.

Non-volatile memory using a reduced number of interconnect terminals

In one embodiment, an apparatus includes: an interface controller to receive a request from an external device coupled to the apparatus to access a flash memory coupled to the apparatus, the request comprising an access request to a replay protection monotonic counter (RPMC) of the flash memory; and a flash controller coupled to the interface controller. In turn, the flash controller includes: an atomic sequencer to arbitrate accesses to the RPMC by a plurality of components; and a mapper to map the access request to a selected counter of the RPMC associated with the external device. Other embodiments are described and claimed.

System, apparatus and method for replay protection for a platform component

A method implemented by a system on a chip (SOC) system executing an enhance serial peripheral interconnect (eSPI) master. The method to receive an alert from an eSPI slave, send a get out of band message to the eSPI slave, and receive an out of band message from the eSPI slave including a connection or disconnection command. The method enabling the SOC to include an embedded multiplexor for managing the role of a universal serial bus (USB) Type-C connector.

Inband messaging method for integrated type-C universal serial bus detection using enhanced serial peripheral interconnect

Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.

Growing community of inventors

Folsom, CA, United States of America

Zhenyu Zhu