Globalfoundries Inc.

Globalfoundries U.S. Inc.

Zhenyu Hu

Hong Yu

Haiting Wang

Hui Zang

Hongliang Shen

Hsien-Ching Lo

Richard J Carter

Wei Zhao

Andy C Wei

Wei Hong

Xinyuan Dou

Xing Zhang

Judson Robert Holt

Jinping Liu

Jagar Singh

Xusheng Kevin Wu

Alexander M Derrickson

Qi Zhang

Scott Beasor

Daniel T Pham

Liu Jiang

Sruthi Muralidharan

Ruilong Xie

Vibhor Jain

Shesh Mani Pandey

Yi Qi

Jin Ping Liu

Nicholas V Licausi

George Robert Mulfinger

Jianwei Peng

Zhao Lun

Alexander Lee Martin

Tao Han

Hui Zhan

Ashish Kumar Jha

Pei Zhao

Amy L Child

Andreas Knorr

Julien Frougier

Min-Hwa Chi

John Joseph Pekarik

Jiehui Shu

Sipeng Gu

Joseph Francis Shepard, Jr

Navneet Jain

David C Pritchard

Jerome Ciavatti

Tamilmani Ethirajan

Jae Gon Lee

Lun Zhao

Erik Geiss

Tung-Hsing Lee

Alina Vinslava

Edward Reis

Sang Woo Lim

Tae Jeong Lee

Kyung-Bum Koo

Charles Vanleuvan

Emilie M S Bourjot

A structure is provided, the structure comprising a substrate and a first silicon germanium fin over the substrate. A first silicon germanium layer may be arranged in the substrate, whereby the first silicon germanium layer may be coupled to the first silicon germanium fin. A second silicon germanium layer may be arranged in the substrate, whereby the second silicon germanium layer may be coupled to the first silicon germanium fin.

Silicon germanium fins and integration methods

Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer includes a portion between the second dielectric layer and a semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a gate electrode on the layer stack. The gate electrode is laterally between the first and second source/drain regions, and the gate electrode overlaps with the portion of the first dielectric layer and the second dielectric layer. The structure further comprises a spacer laterally between the first source/drain region and the second dielectric layer.

Device structures for a high-voltage semiconductor device

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a collector having a first semiconductor layer, an emitter having a second semiconductor layer, an intrinsic base including nanosheet channel layers positioned with a spaced arrangement in a layer stack, and a base contact laterally positioned between the first and second semiconductor layers. Each nanosheet channel layer extends laterally from the first semiconductor layer to the second semiconductor layer. Sections of the base contact are respectively positioned in spaces between the nanosheet channel layers. The structure further includes first spacers laterally positioned between the sections of the base contact and the first semiconductor layer, and second spacers laterally positioned between the sections of the base contact and the second semiconductor layer.

Bipolar junction transistors with a nanosheet intrinsic base

A structure is provided, the structure may include an active layer arranged over a buried oxide layer, the active layer having a top surface. The top surface of the active layer may have a first portion and a second portion. A barrier stack may be arranged over the first portion of the top surface of the active layer. The barrier stack may include a barrier layer. The second portion of the top surface of the active layer may be adjacent to the barrier stack. A fin may be spaced from the first portion of the top surface of the active layer by the barrier stack, the fin having a first side surface, a second side surface opposite to the first side surface and a top surface. A dielectric layer may be arranged on the first side surface, the second side surface and the top surface of the fin, and the second portion of the top surface of the active layer. A metal layer may be arranged over the dielectric layer.

Fin on silicon-on-insulator

Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.

High-voltage semiconductor device structures

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Lateral bipolar transistor

The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

Single fin structures

Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

Lateral bipolar transistor structure with base layer of varying horizontal width and methods to form same

In a disclosed semiconductor structure, a lateral bipolar junction transistor (BJT) has a base positioned laterally between a collector and an emitter. The base includes a semiconductor fin with a first portion that extends from a substrate through an isolation layer, a second portion on the first portion, and a third portion on the second portion. The collector and emitter are on the isolation layer and positioned laterally immediately adjacent to opposing sidewalls of the second portion of the semiconductor fin. In some embodiments, the BJT is a standard BJT where the semiconductor fin (i.e., the base), the collector, and the emitter are made of the same semiconductor material. In other embodiments, the BJT is a heterojunction bipolar transistor (HBT) where a section of the semiconductor fin (i.e., the base) is made of a different semiconductor material for improved performance. Also disclosed is a method of forming the structure.

Fin-based lateral bipolar junction transistor and method

The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

Lateral bipolar transistor structure with base over semiconductor buffer and related method

One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

Lateral bipolar junction transistor device and method of making such a device

The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.

Single diffusion break device for FDSOI

Growing community of inventors

Clifton Park, NY, United States of America

Zhenyu Hu