Gowin Semiconductor Corporation

Other

Zhenyu Gu

Jinghui Zhu

Jianhua Liu

Chienkuang Chen

Diwakar Chopperla

Ning Song

Xiaozhi Lin

Tianping Wang

Tianxin Wang

Jinsu Chen

Zhangheng Xue

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Method and system for organizing programmable semiconductor device into multiple clock regions

The present disclosure provides a medicine box, including a housing, a door, a first clamping member, and a second clamping member, a cavity is formed inside the housing, the housing has an opening on a top surface; an end of the door is rotatably connected with one side of the housing at the opening, an end of the first clamping member is connected with the other end of the door, and the other end of the first clamping member includes a first magnetic portion; an end of the second clamping member is connected with the other side of the housing at the opening, and the other end of the second clamping member includes a second magnetic portion; and a clamping area with a changeable size is formed between the first magnetic portion and the second magnetic portion.

Medicine box

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer ('SerDes') region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions

A field-programmable gate array ('FPGA') contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals ('RCSs') generated from a clock source with a high clock signal quality (&#x201c;CSQ&#x201d;) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (&#x201c;NCSs&#x201d;) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (&#x201c;SCSs&#x201d;) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

Methods and apparatus for providing a clock fabric for an FPGA organized in multiple clock regions

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Shanghai, China

Zhenyu Gu