Qualcomm Incorporated

ZhenQi Chen

Helena Deirdre O'Shea

Scott Davenport

Richard Dominic Wietfeldt

Lalan Jee Mishra

Umesh Srikantiah

Xiangdong Zhang

Wolfgang Roethig

Xinwei Wang

Yan Kit Gary Hau

Zhenying Luo

Jing-Hwa Chen

Yanjie Sun

Reza Rodd

Chiew-Guan Tan

Christopher Kong Yee Chun

Wilson Jianbo Chen

Jianguo Yao

Jisun Ryu

Reza Mohammadpourrad

Tianzuo Xi

Haichuan Kang

Ashwin Duggal

Kihun Chang

Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.

Controlling the application time of radio frequency front end triggers based on execution of sequences

Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

Intra-module serial communication interface for radio frequency devices

Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

On-chip clock generator calibration

Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Asynchronous interrupt with synchronous polling and inhibit options on an RFFE bus

Systems, methods, and apparatus for functionally extending a capability of a write datagram for RFFE and SPMI devices are provided. A sending device sets a configuration register to indicate an operation mode of a write command and generates a command code field in the write command. A most significant bit of the command code field has a value of 1 and remaining bits of the command code field are defined based on the operation mode. The sending device further includes payload bytes in a payload field of the write command based on the operation mode and sends the write command to a receiver via a bus interface. The sending device may also set a page-address register to include a page-address to be used if page segmented access (PSA) is enabled for the write command and set the configuration register to indicate whether the PSA for the write command is enabled.

Technique for RFFE and SPMI register-0 write datagram functional extension

A circuit including a radio frequency (RF) amplifier including a transistor configured to receive an RF signal at its control terminal, a capacitor coupled to a first terminal of the transistor, an inductor coupled to a second terminal of the transistor, wherein the capacitor and inductor form a loop from the first terminal to the second terminal, wherein the loop bypasses a parasitic inductance between the second terminal and ground.

Systems and methods providing a matching circuit that bypasses a parasitic impedance

Certain aspects of the present disclosure provide methods and apparatus for operating a power amplifier. In one example, the apparatus includes a power amplifier configured to amplify an input signal having a frequency to produce a radio frequency (RF) output signal at an output and a harmonic tuning circuit coupled between a power supply and the power amplifier output, the harmonic tuning circuit configured to reduce a current or voltage provided to the power amplifier via a resonance at one or more harmonics of the frequency of the input signal.

Methods and apparatuses for ruggedizing a power amplifier against breakdown using harmonic tuning

Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.

Radio frequency front end devices with masked write

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ZhenQi Chen