Sandisk Technologies Inc.

Zhenni Wan

Bo Lei

Nidhi Agrawal

Jiahui Yuan

Yu-Chung Lien

Jun Wan

Ravi J Kumar

Xue Bai Pitner

Huiwen Xu

Jia Li

Yihang Liu

Peng Wang

During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.

Non-volatile memory with overdrive voltage zoning to compensate for reduced margins

A memory device includes a memory block comprising a plurality of memory cells and control circuitry configured to perform a read level acquisition operation to determine optimal read levels for reading a plurality of data states of the plurality of memory cells. To perform the read level acquisition operation, the control circuitry is configured to supply a read level acquisition waveform to the plurality of memory cells, obtain data miss compare (DMC) values for the plurality of memory cells based on the read level acquisition waveform, and identify the optimal read levels for the plurality of data states based on the DMC values. The control circuitry is further configured to perform a read operation on the plurality of memory cells in accordance with the optimal read levels as identified based on the DMC values.

Binary read-based fast algorithm for optimal read level acquisition

A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.

Adaptive single-side erase to improve cell reliability

The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.

Techniques for reading memory cells in a memory device during a multi-pass programming operation

The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

Verify techniques for current reduction in a memory device

A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and increase efficiency.

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San Jose, CA, United States of America

Zhenni Wan