Micron Technology Incorporated

Sandisk Technologies Inc.

Zhenming Zhou

Murong Lang

Tingjun Xie

Yu-Chung Lien

Zhenlei Shen

Zhongguang Xu

Jian Huang

Jiangli Zhu

Ching-Huang Lu

Li-Te Chang

Seungjune Jeon

Deepanshu Dutta

Dana Lee

Mikai Chen

Wei Wang

Charles See Yeung Kwong

Nagendra Prasad Ganesh Rao

Peng Zhang

Gerrit Jan Hemink

Jun Wan

Fangfang Zhu

Guirong Liang

Wenzhou Chen

Frederick Adi

Masaaki Higashitani

Ying Yu Tai

Henry Chin

Ting Luo

Christina Papagianni

Sead Zildzic, Jr

Xiang Yang

Jianmin Huang

Zhengang Chen

Yang Lu

Bo Lei

Pitamber Shukla

Chih-Kuo Kao

Tomer Eliash

Yi-Chieh Chen

Lei Lin

Ronit Roneel Prakash

Vamsi Pavan Rayaprolu

Huai-Yuan Tseng

Jung Sheng Hoei

Xiangang Luo

Dengtao Zhao

Michael G Miller

Mohan Dunga

Gautam Ashok Dusija

Aaron Lee

Xiying Costa

Juane Li

Sarath Chandran Puthenthermadam

Mrinal Kochar

Chris Nga Yee Avila

Guang Hu

Charles S Kwong

Arash Hazeghi

Vivek Shivhare

Sead Zildzic

Vinh Q Diep

Paing Z Htet

Cynthia Hua-Ling Hsu

Chandu Gorla

Thomas Fiala

Hanping Chen

Joshua Garrison

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to modify pulses used to program memory components. The controller receives a request to program data in an individual memory component of a set of memory components. The controller computes a plurality of memory reliability criteria associated with the individual memory component and compares the plurality of memory reliability criteria to one or more threshold values. The controller selects a program pulse used to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more threshold values.

Program pulse modification

Methods, apparatuses and systems related to managing read levels across multiple groupings or decks are described. The apparatus may include a read level management mechanism configured to controls or dynamically adjusts the read levels for the different groupings according to a real-time condition/measure associated with the programming delays.

Apparatus with multi-deck read level management and methods for operating the same

Methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. The portion of memory is erased in response to determining that the portion of memory is invalid. A request to move an additional portion of memory to a free pool from the garbage pool is received. A free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. The erased portion of memory is moved from the garbage pool to the free pool.

Optimizing data reliability using erase retention

A block of a memory device is identified. A threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. The threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a difference between the wordline and a boundary wordline of the block. A read operations is performed on the block using a read level voltage modified by the threshold voltage offset, wherein the read level voltage is associated with the block.

Error avoidance for partially programmed blocks of a memory device

A first blocks of a set of blocks of a memory device is identified. A die on which the first block resides is identified among a plurality of dies of the memory device. A threshold value associated with the die is selected from a range associated with a projected reliability metric of the die. Responsive to determining that an endurance metric value associated with the die matches the threshold value, a program operation is performed with respect to a second block of the set of blocks.

Adaptive wear leveling for endurance compensation

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: identifying a block of the memory device, the block spanning over a plurality of decks; determining whether a set of memory cells of the memory device is disposed in a first deck of the block or a second deck of the block, the first deck having a memory reliability metric satisfying a first criterion pertaining to a reliability of a deck, and the second deck having a memory reliability metric not satisfying the first criterion; selecting, based on the determination, an erase policy for performing an erase operation with respect to the set of memory cells; and causing the erase operation to be performed with respect to the set of memory cells in accordance with the erase policy.

Selection of erase policy in a memory device

A system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. The operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. The operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.

Dynamic read calibration

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to generate virtual or superblocks using multiple partial good blocks. The controller identifies a first partial good block (PGB) in a set of memory components, the first PGB having first subset of word line groups (WGRs) that are categorized as being non-defective. The controller searches for a second PGB in the set of memory components having a second subset of WGRs that are categorized as being non-defective. The controller computes a total quantity of WGRs based on the first quantity of WGRs in the first subset of WGRs and a second quantity of WGRs in the second subset of WGRs and, in response, combines the first PGB and the second PGB to form an individual virtual block.

Generating virtual blocks using partial good blocks

Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

Adaptive sensing time for memory operations

Methods, systems, and apparatuses include determining an erase policy for a memory device. An erase operation is selected based on the determined erase policy, where the erase operations include an alternating erase operation and a uniform erase operation. The erase operation is executed on a portion of memory.

Dynamic erase operation selection using erase policy

A processing device is operatively coupled to an array of memory cells. The processing device determines that a media endurance metric value for a string of the array of memory cells satisfies a first threshold criterion based on a first threshold value. The processing device further controls, based on the media endurance metric value, a ramp rate of a program pulse applied to a wordline of the string.

Single-level cell programming with adaptive wordline ramp rate

A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event in the memory sub-system, and in response, identifies a memory die of a plurality of memory dies in the memory sub-system. The processing device further determines a read margin associated with a first distribution of memory cells of the identified memory die, and determines an adaptive scan frequency for the identified memory die based on the read margin associated with the first distribution of memory cells.

Adaptive integrity scan in a memory sub-system

A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

Low stress refresh erase in a memory device

A method for receiving a request for performing a programming operation on one or more memory blocks of a memory device, identifying a value of a media endurance metric associated with the one or more memory blocks, determining a programming voltage offset corresponding to the value of the media endurance metric, and performing, using the programming voltage offset, the programming operation on the one or more memory blocks. The method further includes identifying a program-verify voltage level associated with the one or more memory blocks, determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric, and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.

Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices

Aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. The controller selects a portion of the set of memory components that is empty and ready to be programmed. The controller reads one or more signals from the selected portion of the set of memory components. The controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. The controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.

Empty page scan operations adjustment

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San Jose, CA, United States of America

Zhenming Zhou