Micron Technology Incorporated

Sandisk Technologies Inc.

Zhenming Zhou

Murong Lang

Tingjun Xie

Yu-Chung Lien

Zhenlei Shen

Zhongguang Xu

Jian Huang

Jiangli Zhu

Li-Te Chang

Ching-Huang Lu

Seungjune Jeon

Deepanshu Dutta

Dana Lee

Wei Wang

Charles See Yeung Kwong

Mikai Chen

Peng Zhang

Nagendra Prasad Ganesh Rao

Gerrit Jan Hemink

Jun Wan

Fangfang Zhu

Guirong Liang

Wenzhou Chen

Frederick Adi

Lei Lin

Masaaki Higashitani

Zhengang Chen

Ying Yu Tai

Henry Chin

Ting Luo

Christina Papagianni

Sead Zildzic, Jr

Xiang Yang

Jianmin Huang

Yang Lu

Bo Lei

Pitamber Shukla

Chih-Kuo Kao

Tomer Eliash

Yi-Chieh Chen

Ronit Roneel Prakash

Vamsi Pavan Rayaprolu

Huai-Yuan Tseng

Jung Sheng Hoei

Xiangang Luo

Dengtao Zhao

Mohan Dunga

Michael G Miller

Gautam Ashok Dusija

Aaron Lee

Xiying Costa

Juane Li

Sarath Chandran Puthenthermadam

Mrinal Kochar

Chris Nga Yee Avila

Guang Hu

Charles S Kwong

Arash Hazeghi

Vivek Shivhare

Vinh Q Diep

Sead Zildzic

Paing Z Htet

Cynthia Hua-Ling Hsu

Chandu Gorla

Thomas Fiala

Hanping Chen

Joshua Garrison

A processing device in a memory sub-system determines one or more read margin levels associated with the memory device. A machine learning model is applied to the one or more read margin levels to generate a read margin prediction value associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.

Adaptive scanning of memory devices with supervised learning

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a first read level offset associated with reading a first set of data from a first level using a first read level of a plurality of read levels. The controller applies the first read level offset to a machine learning model to estimate a second read level offset, associated with reading a second set of data from a second level of the plurality of levels, using a second read level of the plurality of read levels. The controller updates, based on the first read level offset and the estimated second read level offset, a look-up table that includes a set of read level offsets used to read data from the plurality of levels of the individual component.

Model based error avoidance

An example includes a method for performing a block family (BF) scan operation of a memory device. The method includes performing a first block family error avoidance (BFEA) scan via a controller on a wordline of a first fractional good block of a virtual block. The method also includes performing a second BFEA scan via the controller on a wordline of a second fractional good block of the virtual block. The method also includes determining a BF bin number for each of the first and second fractional good blocks via the controller based on the first and second BFEA scans. The method further includes refreshing data stored in the virtual block via the controller based on the respective BF bin numbers of the first and second fractional good blocks.

Block family management for a virtual block

In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.

Power loss error detection using partial block handling

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to modify pulses used to program memory components. The controller receives a request to program data in an individual memory component of a set of memory components. The controller computes a plurality of memory reliability criteria associated with the individual memory component and compares the plurality of memory reliability criteria to one or more threshold values. The controller selects a program pulse used to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more threshold values.

Program pulse modification

Methods, apparatuses and systems related to managing read levels across multiple groupings or decks are described. The apparatus may include a read level management mechanism configured to controls or dynamically adjusts the read levels for the different groupings according to a real-time condition/measure associated with the programming delays.

Apparatus with multi-deck read level management and methods for operating the same

Methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. The portion of memory is erased in response to determining that the portion of memory is invalid. A request to move an additional portion of memory to a free pool from the garbage pool is received. A free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. The erased portion of memory is moved from the garbage pool to the free pool.

Optimizing data reliability using erase retention

A block of a memory device is identified. A threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. The threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a difference between the wordline and a boundary wordline of the block. A read operations is performed on the block using a read level voltage modified by the threshold voltage offset, wherein the read level voltage is associated with the block.

Error avoidance for partially programmed blocks of a memory device

A first blocks of a set of blocks of a memory device is identified. A die on which the first block resides is identified among a plurality of dies of the memory device. A threshold value associated with the die is selected from a range associated with a projected reliability metric of the die. Responsive to determining that an endurance metric value associated with the die matches the threshold value, a program operation is performed with respect to a second block of the set of blocks.

Adaptive wear leveling for endurance compensation

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: identifying a block of the memory device, the block spanning over a plurality of decks; determining whether a set of memory cells of the memory device is disposed in a first deck of the block or a second deck of the block, the first deck having a memory reliability metric satisfying a first criterion pertaining to a reliability of a deck, and the second deck having a memory reliability metric not satisfying the first criterion; selecting, based on the determination, an erase policy for performing an erase operation with respect to the set of memory cells; and causing the erase operation to be performed with respect to the set of memory cells in accordance with the erase policy.

Selection of erase policy in a memory device

A system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. The operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. The operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.

Dynamic read calibration

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to generate virtual or superblocks using multiple partial good blocks. The controller identifies a first partial good block (PGB) in a set of memory components, the first PGB having first subset of word line groups (WGRs) that are categorized as being non-defective. The controller searches for a second PGB in the set of memory components having a second subset of WGRs that are categorized as being non-defective. The controller computes a total quantity of WGRs based on the first quantity of WGRs in the first subset of WGRs and a second quantity of WGRs in the second subset of WGRs and, in response, combines the first PGB and the second PGB to form an individual virtual block.

Generating virtual blocks using partial good blocks

Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

Adaptive sensing time for memory operations

Methods, systems, and apparatuses include determining an erase policy for a memory device. An erase operation is selected based on the determined erase policy, where the erase operations include an alternating erase operation and a uniform erase operation. The erase operation is executed on a portion of memory.

Dynamic erase operation selection using erase policy

A processing device is operatively coupled to an array of memory cells. The processing device determines that a media endurance metric value for a string of the array of memory cells satisfies a first threshold criterion based on a first threshold value. The processing device further controls, based on the media endurance metric value, a ramp rate of a program pulse applied to a wordline of the string.

Single-level cell programming with adaptive wordline ramp rate

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San Jose, CA, United States of America

Zhenming Zhou