Advanced Micro Devices Corporation

Legerity, Inc.

Zhenhua Liu

Yi Cheng

Kris Martin Holt

Thomas Jefferson Ronaldue

A transmitter within a line driver circuit is configured to supply data pulses over existing residential wiring. The transmitter is implemented in a CMOS integrated circuit. The transmitter comprises three stages: a front-end digital/analog convertor (DAC), an intermediate DAC, and a current amplifier. The first stage dictates whether the output signal is in high power mode or low power mode. The intermediate DAC, as the second stage, controls the waveform shape and tunes the edge rate, thereby outputting a positive current signal and a negative current signal. The final stage amplifies these current signals to yield current signals having a desired waveform shape, power mode, and edge rate.

Apparatus and method for a PHY transmitter with programmable power mode control in CMOS

A CMOS device for generating a waveformn envelope is provided in a network that uses a twisted pair medium, such as a telephone line, to connect stations. The CMOS device receives analog signals representing pulsed data signals sent over the telephone line and generates an envelope waveform for the received analog signal. The envelope waveform can then be used to detect the arrival of data, as opposed to noise on the network.

Apparatus and method for generating an envelope for data signals using

An improved decoder for recovering Non-Return-to-Zero Interface (NRZI) digital data from a multiple layer transition (MLT-3) encoded signal in a 100BASE-TX Ethernet (IEEE Standard 802.3u) uses multiple comparators to minimize jitter in the decoded signal. A CMOS-based biasing circuit receives the differential MLT-3 encoded input signals and control signals from a signal amplitude detection circuit. The biasing circuit adjusts for any DC offset, and also generates offset signals based on respective mid-peak voltage values of the respective differential input signals. Four comparators are then used to detect a prescribed edge transition (e.g., a positive edge) coinciding with the respective mid-peak voltage value in the respective signals. The detected edge transitions are then used by edge decoding logic to generate the NRZI bilevel signal.

Apparatus and method for decoding differential multi-level data with

A cable length estimation circuit for receiving an input MLT-3 signal provided through an arbitrary length cable and providing a control signal to an equalizer indicating the estimated length of the cable enabling the equalizer to compensate for distortion of the MLT-3 signal resulting from the cable. The cable length estimation circuit includes an edge rate detection circuit for measuring the rate of change in voltage with respect to time during transitions of the MLT-3 signal to provide an indication of cable length. The cable length estimation circuit can also include a digital averaging circuit which provides an average value for signals from the edge rate detection circuit for a desired number of transitions of the MLT-3 signal. The cable length estimation can also include a baseline wander detection circuit which functions so that previous cable length estimations are provided when baseline wander is detected.

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Sunnyvale, CA, United States of America

Zhenhua Liu