Qualcomm Incorporated

Zhengzheng Wu

Chao Song

Karthik Nagarajan

Jeffrey Mark Hinrichs

Marzio Pedrali-Noy

Xuhao Huang

Xu Zhang

Deping Huang

Ye Lu

Haitao Cheng

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

Power and area efficient digital-to-time converter with improved stability

A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay.

Digital phase-frequency detector with split control loops for low jitter and fast locking

A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

Method of generating precise and PVT-stable time delay or frequency using CMOS circuits

A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation

A load circuit of a low-dropout (LDO) regulator is disclosed herein according to certain aspects. The load circuit includes a field effect transistor having a source coupled to a supply rail, a gate, and a drain coupled to a gate of a pass transistor of the LDO regulator. The load circuit also includes an adjustable voltage source coupled between the drain and the gate of the field effect transistor, and a voltage control circuit configured to detect a change in a current load through the pass transistor, and to adjust a voltage of the adjustable voltage source based on the detected change in the current load.

Adaptive gate-biased field effect transistor for low-dropout regulator

A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

In certain aspects, an integrated circuit comprises a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance. The integrated circuit also comprises a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor have a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation.

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Santa Clara, CA, United States of America

Zhengzheng Wu