International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Zhengwen O Li

Fei Liu

Qing Cao

Kangguo Cheng

Zhen Zhang

Chengwen Pei

Jian Yu

Huilong Zhu

Keith Kwong Hon Wong

Lawrence Alfred Clevenger

Dechao Guo

Unoh Kwon

Brian Christopher Sapp

Filippos Papadatos

Carl John Radens

Kevin Shawn Petrarca

Rainer Klaus Krause

Tien-Jen Cheng

Mukta G Farooq

Zhijiong Luo

Christian Lavoie

Michael Patrick Chudzik

Ahmet Serkan Ozcan

Harold John Hovel

Yan Zun Li

Shu-Jen Han

Reinaldo Ariel Vega

Jeffrey Bowman Johnson

Emre Alptekin

Roger Allan Quon

Jun Yuan

Yanfeng Wang

Kevin M Prettyman

Randolph F Knarr

Kejia Wang

Gerd Pfeiffer

Gan Wang

Vijay Narayanan

Richard Stephan Wise

Andrew Herbert Simon

Ravikumar Ramachandran

Yu Zhu

Michael John Hargrove

Hongwen Yan

Oh-Jung Kwon

Wing L Lai

Naoyoshi Kusaba

Ramachandra Divakaruni

Mark R Visokay

Damon B Farmer

Siddarth A Krishnan

Viraj Yashawant Sardesai

Abhishek Dube

Stephan Grunow

Sunfei Fang

Keith Howard Tabakman

Dan Moy

Cung D Tran

Hari V Mallela

Sameer Hemchand Jain

Frank Bin Yang

Antonio L P Rotondaro

Ayse M Ozbek

Ranier Krauser

A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

Piezoelectric vacuum transistor

A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed channel region. An electrolyte gel is disposed between the gate electrode and the exposed channel region, wherein ions are immobilized in the electrolyte gel below a transition temperature and mobilized above the transition temperature to increase device resistance.

On-chip integrated temperature protection device based on gel electrolyte

An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.

FDSOI with on-chip physically unclonable function

A three-dimensional integration of synapse circuitry is formed. One or more neuron layers each comprises a plurality of computing elements, and one or more synapse layers each comprising an array of memory elements are formed on top of the one or more neuron layers. A plurality of staggered through-silicon vias (TSVs) connect the one or more neuron layers to the one or more synapse layers and operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers.

Three-dimensional integration of neurosynaptic chips

A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively.

Nanoparticle with plural functionalities, and method of forming the nanoparticle

The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Secure semiconductor chip by piezoelectricity

A sensor includes a semiconductor substrate having first pointed nodes extending into a channel from a first side of the channel. Second pointed nodes extend into the channel from a second side of the channel, which is opposite the first side. The second pointed nodes being self-aligned to the first pointed nodes on the opposite side of the channel. The first pointed nodes and the second pointed nodes are connected to a circuit to detect particles in the channel.

High density nano-array for sensing

A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric reactant; and a sealant layer arranged on a surface of the self-destructive layer, on sidewalls of the self-destructive layer, and on the chip substrate such that the sealant layer forms a package seal on the semiconductor chip; wherein the pyrophoric reactant ignites spontaneously upon exposure to air.

Prevention of reverse engineering of security chips

A method of forming a nanoparticle includes forming a layer of semiconductor material on a substrate, forming a first layer on the semiconductor material, and etching the semiconductor layer to form the nanoparticle including the first layer on a first side of the nanoparticle and the semiconductor material on a second side of the nanoparticle.

A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.

Dielectric thermal conductor for passivating eFuse and metal resistor

A dosimetry device includes a first chamber formed on a substrate with a first decomposable barrier sensitive to radiation and a first chemical component. A second chamber is formed on the substrate in proximity of the first chamber and includes a second decomposable barrier sensitive to radiation and a second chemical component. Upon a radiation event, decomposition of the first and second barriers of the first and second chambers permits a mixing of the first and second chemical components to cause a visible change of the dosimetry device.

Colorimetric radiation dosimetry

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Austin, TX, United States of America

Zhengwen O Li