Boe Technology Group Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Zhengwei Chen

Zhenfei Cai

Xingxing Song

Chaohuan Hsu

Guoquan Liu

Jian Ye Chen

Qiuping Huang

Jianshe Xue

Xingfeng Ren

Dongseob Kim

Jaemoon Chung

Qiangqiang Ji

Seong Sil Im

Chao-Huan Hsu

Huawei Xu

A method for manufacturing a display panel, a display panel, and a display device are provided. The method includes: forming a plurality of gate lines and a common electrode line pattern on a base substrate; forming an insulating layer on the base substrate on which the plurality of gate lines and the common electrode line pattern are formed; forming a via hole on the insulating layer; and forming a metal conductive pattern on the base substrate on which the insulating layer is formed. The common electrode line and the common electrode connection block located on two sides of a gate line are electrically connected through a bridging structure in a conductive layer made of metal, which reduces the resistance of the bridging structure, so that the voltage uniformity throughout the common electrode line pattern which is bridged through the bridging pattern is high.

Method for manufacturing display panel, display panel, and display device

The present application discloses a display substrate comprising a base substrate; a first electrode on the base substrate; a first insulating layer on a side of the first electrode distal to the base substrate; a thin film transistor on a side of the first insulating layer distal to the first electrode; a second insulating layer on a side of the thin film transistor distal to the first insulating layer; an organic layer on a side of the second insulating layer distal to the thin film transistor; and a second electrode on a side of the organic layer distal to the second insulating layer.

Display substrate, liquid crystal display panel and display apparatus having the same, and fabricating method thereof

A method for producing an array substrate is provided. The method includes: forming metal film layers and patterning the metal film layers to form a plurality rows of gate lines and a plurality columns of data lines crossed to each other in the non-display area and forming thin film transistors; forming a pad part at one end of the gate lines or data lines. The process of producing the pad part includes: forming a first insulation layer on the metal film layers by patterning; forming an etching protection layer, a source and drain metal layer and a second insulation layer sequentially by patterning, wherein the first insulation layer, the etching protection layer, the source and drain metal layer and the second insulation layer form a trapezoid stack.

Array substrate, method for producing the same and display apparatus

The present disclosure discloses an array substrate including a display area and a data lead area. The display area includes data signal lines and gate lines. The data lead area includes peripheral wirings connecting the data signal lines and wiring terminals. The peripheral wirings include a plurality of metal traces which are corresponding to the data signal lines in a one-to-one manner and manufactured from a same layer as the gate lines. Each of the metal traces is connected to one of the data signal lines which is corresponding to the each of the metal trace.

Array substrate, method for manufacturing the same and display device

The present disclosure discloses a thin film transistor comprising: an active layer; an etching barrier layer arranged on the active layer and formed with a plurality of via holes therein; and a source electrode and a drain electrode arranged on the etching barrier layer, wherein the source electrode comprises at least two sub source electrodes and the drain electrode comprises at least two sub drain electrodes; and the sub source electrodes and the sub drain electrodes constitute at least two parallel sub-switches, each of which comprises a sub source electrode and a sub drain electrode, and the sub source electrode and the sub drain electrode are electrically connected to the active layer through the via holes in the etching barrier layer, respectively. The present disclosure further discloses a method of manufacturing a thin film transistor, an array substrate and a display apparatus. The present disclosure employs a multi-channel design with which the DGS problem due to an incomplete active layer is solved by using a plurality of parallel sub-switches, ensuring the normal operation of the pixel and thus increasing yield and useful life of product.

Thin film transistor and method of manufacturing the same, array substrate and display apparatus

The present invention relates to the technical field of display, and in particular to a post spacer, a display panel and a display device. The post spacer includes a support post and a support pillow, wherein the support pillow is formed of a plurality of sub-pillows dispersedly arranged below the bottom of the support post. Since the post spacer is provided with the support pillows dispersedly arranged below the bottom of the support post, the bottom of the support post can be more uniformly stressed, and the support pillow can further provide a certain antiskid effect. Therefore, the post spacer of the present invention has a better supporting effect and can effectively avoid Mura faults.

Post spacer, display panel and display device

The present disclosure provides a display substrate, its testing method and its manufacturing method. A first testing terminal is connected to a gate electrode of a first TFT, a second testing terminal is connected to a source electrode of the first TFT and a drain electrode of a second TFT, a third testing terminal is connected to a gate electrode of the second TFT, and a fourth testing terminal is connected to a drain electrode of the first TFT and a source electrode of the second TFT.

Display substrate, its testing method and its manufacturing method

Embodiments of the invention provide a conductive structure, a thin film transistor, an array substrate, and a display device. The conductive structure comprises a copper layer formed of copper or copper alloy; a blocking layer for preventing copper ions of the copper layer from diffusing outward; and a diffusion prevention layer for preventing exterior ions from diffusing to the copper layer and disposed between the copper layer and the blocking layer. The multilayer conductive structure according to an embodiment of the invention can prevent exterior ions from diffusing into a copper layer and prevent copper ions from diffusing outward to reduce ions diffusion that adversely impacts the electricity performance and chemical corrosion resistance of the copper metal layer, and meanwhile can enhance adhesiveness of the conductive structure, which may be helpful for etching/patterning of the multilayer conductive structure.

Thin film transistor array substrate and a thin film transistor which comprise a conductive structure comprising a blocking layer and a diffusion prevention layer

The present invention provides an arrayed substrate, a method for manufacturing the same and a display device. It relates to a field of display technology. The short-circuit defect between the lead wires may be avoided while reducing a spacing between the adjacent two lead lines in a limited space for wiring. The array substrate comprises a plurality of criss-cross gate lines and data lines within a display area, and the array substrate further comprises a first short-circuiting ring and a second short-circuiting ring within a non-display area, and first data lead wires and second data lead wires connected electrically with the first short-circuiting ring and the second short-circuiting ring respectively; the first data lead wires are provided in the same layer and made from the same material as the gate lines for connecting electrically the first short-circuiting ring with first data lines of the data lines; the second data lead wires are provided in the same layer and made from the same material as the data lines for connecting electrically the second short-circuiting ring with second data lines of the data lines; wherein the first data lines are interleaved with the second data lines.

An array substrate comprising display areas and non-display areas is provided. The non-display area comprises an area in which a plurality of gate lines and a plurality of data lines crossed to each other are located and an area in which thin film transistors are located, the gate lines and the data lines being formed by patterning metal film layers which are formed in the area by magnetron sputtering targets spaced to each other; and wherein a pad part is formed in an area of the non-display areas corresponding to the spacing areas between the targets, a sum of thickness of the metal film layer foamed in the areas corresponding to the spacing areas between the targets and the thickness of the pad part being equal to the thickness of the metal film layer formed in the areas facing the targets.

In the present disclosure, it is provided an array substrate including a pad area, signal lines arranged on the substrate, conductive connection lines arranged at least on the pad area and directly connected to a flexible circuit, and conductive connection lines arranged at least on the pad area and directly connected to a flexible circuit. The conductive connection lines may be connected to the signal lines through a via hole, and may include a first wire and a second wire electrically connected to each other. The second wire may be arranged in such a manner that a contact area between the conductive connection lines and the flexible circuit is not less than a predetermined threshold when the flexible circuit is displaced in a first direction relative to the first wire. The first direction may be substantially perpendicular to an extending direction of the first wire.

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Beijing, China

Zhengwei Chen