Samsung Electronics Co., Ltd.

Zhengping Jiang

Woosung Choi

Nuo Xu

Jing Wang

Weiyi Qi

Chihak Ahn

Hesameddin Ilatikhameneh

Hong-Hyun Park

A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A &#x3c;001&#x3e; direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.

Group IV and III-V p-type MOSFET with high hole mobility and method of manufacturing the same

A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

Generic high-dimensional importance sampling methodology

According to one embodiment of the present invention a circuit simulator configured to simulate a degraded output of a circuit including a plurality of transistors includes: a behavioral recurrent neural network configured to receive an input waveform and to compute a circuit output waveform; a feature engine configured to model one or more degraded circuit elements in accordance with an aging time, to receive the circuit output waveform and to output a plurality of degraded features; and a physics recurrent neural network configured to receive the plurality of degraded features from the feature engine and to simulate the degraded output of the circuit.

System and method for circuit simulation based on recurrent neural networks

Growing community of inventors

San Jose, CA, United States of America

Zhengping Jiang