Qualcomm Incorporated

Zhengming Fu

James Thomas Doyle

Nan Chen

Farsheed Mahmoudi

Chuang Zhang

Alan G Lewis

Mark Todorovich

Gregory Bullard

Soo Youn Kim

Nazanin Darbanian

Adam Polak

Jan Christian Huber

Laura Fuentes

Shree Krishna Pandey

Sassan Shahrokhinia

Amirali Shayan Arani

Yi Cao

Jing Ling

Shan Lu

Daroosh Tayebi

Jia Yao

Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

Detection of laser-based security attacks

Techniques for motion detection are presented. An image sensor for motion detection includes a plurality of analog comparators and a two-dimensional pixel array including a plurality of rows of pixels and a plurality of columns of pixels. Each pixel is configured to convert an optical signal on the pixel into an analog signal. The two-dimensional pixel array is organized into a plurality of groups of pixels each associated with a combined group signal determined based on the analog signals from pixels in the group of pixels. Each analog comparator includes two inputs and is used to compare combined group signals generated by two groups of pixels of the plurality of groups of pixels during a same time period to generate a 1-bit inter-pixel digital signal, where each of the two groups of pixels is coupled to a corresponding input of the two inputs of the each analog comparator.

CMOS image sensor on-die motion detection using inter-pixel mesh relationship

Methods, systems, computer-readable media, and apparatuses for image sensors with pixel binning with configurable shared floating diffusion are presented. In one example, an image sensor system includes a plurality of sensor elements; a photo-sensitive layer coupled to the plurality of sensor elements; a plurality of floating diffusion regions in communication with the photo-sensitive layer, each floating diffusion region of the plurality of floating diffusion regions configured to be selectively enabled; and at least one bridge coupled to two floating diffusion regions of the plurality of floating diffusion regions, the bridge configured to be selectively enabled and, when enabled, to allow a transfer of charge between the two floating diffusion regions.

Image sensors having pixel-binning with configurable shared floating diffusion

Methods, systems, computer-readable media, and apparatuses for dynamic pixel binning are presented. In one example, an image sensor system includes a plurality of sensor elements; a plurality of floating diffusion regions in communication with the plurality of sensor elements, each floating diffusion region of the plurality of floating diffusion regions configured to be selectively enabled; and at least one comparison circuit coupled to at least two floating diffusion regions of the plurality of floating diffusion regions, the comparison circuit configured to: receive input signals from the two floating diffusion regions, compare the input signals, and output a comparison signal based on the comparison of the input signals.

Image sensors with dynamic pixel binning

Techniques for direct local binary pattern (LBP) generation are presented. An image sensor for LBP generation includes a variable reference signal generator and a sensor pixel array that can generate events based on optical signals on the sensor pixel array and a reference level from the variable reference signal generator. The image sensor also includes an address encoder that can encode the addresses of the sensor pixels that generate events, and a binary image generator that can create a binary image based on the addresses of the sensor pixels that generate the events at the reference level. The image sensor may also include a local binary pattern generator configured to determine local binary pattern labels for image pixels whose binary value changes from a first binary image at a first reference level to a subsequent second binary image at a next reference level.

Apparatus and method for generating local binary patterns (LBPS)

Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Capacitively-coupled hybrid parallel power supply

Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Hybrid parallel regulator and power supply combination for improved efficiency and droop response with direct current driven output stage attached directly to the load

An apparatus and method are disclosed for providing efficient operation in a feedback loop having a synchronous buck converter. The synchronous buck converter includes a plurality of individually selectable phases, where each of the phases has a plurality of individually selectable and parallel switching legs. The circuit stores information that associates multiple different load values with respective configuration settings that each define a number of phases and a number of switching legs. As the load changes, the circuit measures the load and selects an appropriate configuration setting. The circuit applies the selected configuration setting to operate the number of phases and a number of parallel switching legs in the buck converter.

Circuits and methods providing high efficiency over a wide range of load values

In one embodiment, a method for measuring current is described herein. The method comprises shorting first and second inputs of an amplifying circuit to generate a first output signal, and converting the first output signal into an offset cancelation value. The method also comprises passing a current through a power switch, wherein the current generates a voltage drop across the power switch, applying the voltage drop across the first and second inputs of the amplifying circuit to generate a second output signal, and converting the second output signal into a current value. The method further comprises subtracting the offset cancelation value from the current value to generate an offset-compensated current value.

High-current sensing scheme using drain-source voltage

An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.

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Austin, TX, United States of America

Zhengming Fu