Intel Corporation

Zhengmin Li

Deepak Shashidhar Vembar

Atsuo Kuwahara

Karthik Veeramani

Selvakumar Panneer

Prasoonkumar Surti

Jill MacDonald Boyce

Varghese George

Adam T Lake

Carl S Marshall

Scott R Janus

Vallabhajosyula S Somayazulu

Hugues Labbe

Mike MacPherson

Sherine Abdelhak

Zhijun Lei

Darrel K Palke

Murali Ramadoss

John S Howard

James E Akiyama

Brent E Insko

Anshuman Thakur

Todd M Witter

Arvind S Tomar

Satish Ramanathan

DongHo Hong

Travis T Schluessler

Huimin Chen

Gary Smith

Gary K Smith

Fan Chen

A method includes receiving a request for a transfer of data on a bus of a computing device; determining a direction for the transfer, at least in part based on the request; determining a quantity of data for the transfer, at least in part based on the request; determining a power state for a lane of the bus, at least in part based on the direction and the quantity of data for the transfer; and setting the power state for the lane of the bus.

Per-lane power management of bus interconnects

One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

Graphics architecture including a neural network pipeline

Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.

Switchable image source in a hybrid graphics systems

An apparatus and method for efficiently improving virtual/real interactions in augmented reality. For example, one embodiment of a method comprises: capturing a raw image including depth data; identifying one or more regions of interest based on a detected spatial proximity of one or more virtual objects and one or more real objects; generating a super-resolution map of the one or more regions of interest using machine-learning techniques or results thereof; detecting interactions between the virtual objects and the real objects using the super-resolution map; and performing one or more graphics processing or general purpose processing operations based on the detected interactions.

Super-resolution apparatus and method for virtual and mixed reality

One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

Computers for supporting multiple virtual reality (VR) display devices and related methods are described herein. An example computer includes a graphics processing unit (GPU) to render frames for a first VR display device and a second VR display device, a memory to store frames rendered by the GPU for the first VR display device and the second VR display device, and a vertical synchronization (VSYNC) scheduler to transmit alternating first and second VSYNC signals to the GPU such that a time period between each of the first or second VSYNC signals and a subsequent one of the first or second VSYNC signals is substantially the same. The GPU is to, based on the first and second VSYNC signals, alternate between rendering a frame for the first VR display device and a frame for the second VR display device.

Computers for supporting multiple virtual reality display devices and related methods

An embodiment of a semiconductor package apparatus may include technology to identify a region of interest portion of a first image, and render the region of interest portion with super-resolution. Other embodiments are disclosed and claimed.

Super-resolution based foveated rendering

Growing community of inventors

Hillsboro, OR, United States of America

Zhengmin Li