Teleputers, LLC

Nvidia Corporation

Samsung Electronics Co., Ltd.

Zhenghong Wang

Ruby B Lee

Ziyad Sami Hakura

A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory.

Cache memory having enhanced performance and security features

A method for dynamically configuring a graphics pipeline system. The method includes determining an optimal pipeline based on: estimating one or more of memory power consumption and computation power consumption of storing and regenerating intermediate results based on graphics state information and one or more factors; determining granularity for the optimal graphics pipeline configuration based on the graphics state information and the one or more factors; collecting runtime information for primitives from graphics pipeline hardware including factors from tessellation or using graphics state information for determining geometry expansion at an output of one or more shader stages; and determining intermediate results to save from a previous processing pass by comparing memory power consumption needed to save the intermediate results with computation power as well as memory power needed for regenerating the intermediate results in one or more later tile rendering passes.

Dynamically optimized deferred rendering pipeline

A tessellation pipeline includes an alpha phase and a beta phase. The alpha phase includes pre-tessellation processing stages, while the beta phase includes post-tessellation processing stages. A processing unit configured to implement a processing stage in the alpha phase stores input graphics data within a buffer and then copies over that buffer with output graphics data, thereby conserving memory resources. The processing unit may also copy output graphics data directly to a level 2 (L2) cache for beta phase processing by other tessellation pipelines, thereby avoiding the need for fixed function copy-out hardware.

Technique for improving the performance of a tessellation pipeline

Methods for accessing, storing and replacing data in a cache memory are provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory.

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San Jose, CA, United States of America

Zhenghong Wang