Seagate Technology Incorporated

Micron Technology Incorporated

Marvellworld Trade Ltd.

Marvell International Limited

Lsi Corporation

Other

Zhengang Chen

Erich Franz Haratsch

Yunxiang Wu

Tingjun Xie

Yu Cai

Ning Chen

Sivagnanam Parthasarathy

Earl T Cohen

Zhenlei Shen

Sundararajan Sankaranarayanan

Eyal En Gad

Gregory Burd

Abdelhakim Alhussien

Yoav Weinberg

Jiangli Zhu

Jianmin Huang

Shashi Kiran Chilappagari

Jeremy Werner

Xueshi Yang

Ying Yu Tai

Charles See Yeung Kwong

Mustafa Nazmi Kaynak

Stephen D Hanna

AbdelHakim S Alhussien

David Patmore

Yingji Ju

Zhenming Zhou

Xiangang Luo

Yingquan Wu

Seungjune Jeon

Wei Wang

Dung Viet Nguyen

Alex G Tang

Sai Krishna Mylavarapu

Charles S Kwong

Cheng Yuan Wu

Mikai Chen

Abdel-Hakim S Alhussien

Lei Lin

Peng Zhang

Meysam Asadi

Zhimin Dong

Wei Wu

Patrick Robert Khayat

Panu Chaichanavong

Murong Lang

Ting Luo

Deping He

Hao Zhong

Gordon James Coleman

Phong Sy Nguyen

Pitamber Shukla

Tao Liu

Ivana Djurdjevic

Guang Hu

Alexander Hubris

Li-Te Chang

Hongmei Xie

Ying Quan Wu

Shantilal Doru

Hope Abigail Henry

Hanping Chen

Steven M Pope

Abdelhakim S Alhussein

Bijan Eskandari-Gharnin

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to modify pulses used to program memory components. The controller receives a request to program data in an individual memory component of a set of memory components. The controller computes a plurality of memory reliability criteria associated with the individual memory component and compares the plurality of memory reliability criteria to one or more threshold values. The controller selects a program pulse used to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more threshold values.

Program pulse modification

Described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.

Memory read calibration based on memory device-originated metrics characterizing voltage distributions

A method for receiving a request for performing a programming operation on one or more memory blocks of a memory device, identifying a value of a media endurance metric associated with the one or more memory blocks, determining a programming voltage offset corresponding to the value of the media endurance metric, and performing, using the programming voltage offset, the programming operation on the one or more memory blocks. The method further includes identifying a program-verify voltage level associated with the one or more memory blocks, determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric, and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.

Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices

A method includes performing a read operation of a first codeword including first hard data and generating an error vector using a reliability metric of the first hard data. The first hard data and error vector are stored in first and second portions of memory. A first corrected codeword is returned that combines the error vector and the hard data from the first and second portions of memory. A read operation of a second codeword is performed, including second hard data and soft information. The hard data and soft information are stored in the first and second portions of memory. A bit of second hard data is flipped responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data. The updated second codeword is returned resulting from reading the portions of memory.

Efficient memory use to support soft information in bit flipping decoders

A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

Early stopping of bit-flip low density parity check decoding based on syndrome weight

A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.

Parity protection in non-volatile memory

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

Self-seeded randomizer for data randomization in flash memory

A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

Power efficient codeword scrambling in a non-volatile memory device

A method may comprise detecting an error associated with accessing a set of data items. The set of data items are programmed to a respective memory page associated with a stripe of a plurality of stripes. In response to determining that the set of data items comprises one or more codewords, a first data recovery process is performed to recover the one or more codewords based at least in part on RAIN redundancy metadata. In response to determining that the set of data items comprises additional parity metadata, a second data recovery process is performed to recover the additional parity metadata based at least in part on LUN redundancy metadata. In response to determining that the set of data items comprises RAIN redundancy metadata, a first data reconstruction process is performed to regenerate the RAIN redundancy metadata based at least in part on one or more sets of codewords.

Redundancy metadata schemes for rain protection of large codewords

In a memory sub-system, data can be received to be stored at a 3-dimensional (3D) memory component in response to a write operation. A first location of a first layer of the 3D memory component is determined at which to store a first portion of the data, where the first layer is within a first logical unit. A second location of a second layer of the 3D memory component is determined at which to store a second portion of the data, where the second layer is within a second logical unit that is different than the first logical unit. The first portion of the data is caused to be stored in first memory cells at the first location within the first layer. The second portion of the data is caused to be stored in second memory cells at the second location within the second layer.

Layer interleaving in multi-layered memory

Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

Corrective read of a memory device with reduced latency

Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting (EC) layout constitutes a first layout in the form of a Latin Square.

Failure-tolerant error correction layout for memory sub-systems

Methods, systems, and devices for a dynamic error control configuration for memory systems are described. The memory system may receive a read command and retrieve a set of data from a location of the memory system based on the read command. The memory system may perform a first type of error control operation on the set of data to determine whether the set of data includes one or more errors. If the set of data includes the one or more errors, the memory system may retrieve a second set of data from the location of the memory system and determine whether a syndrome weight satisfies a threshold. The memory system may perform a second type of error control operation on the second set of data based on determining that the syndrome weight satisfies the threshold.

Dynamic error control configuration for memory systems

A plurality of codewords are programmed to one or more memory pages of a memory sub-system. Each memory page of the memory sub-system is associated with a logical unit of a plurality of logical units of the memory sub-system and at least one of a plane of a plurality of planes of the memory sub-system or a block of a plurality of blocks of the memory sub-system. Each codeword of the plurality of codewords comprises host data and base parity bits. A plurality of additional parity bits are programmed to the one or more memory pages of the memory sub-system, wherein each additional parity bit of the plurality of additional parity bits is associated with a codeword of the plurality of standard codewords. A first set of redundancy metadata is generated corresponding to each of the additional parity bits. The first set of redundancy metadata is programmed to a memory page separate from any memory page storing the additional parity bits.

Redundancy metadata schemes for RAIN protection of large codewords

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, in order to update the meta-data, the meta-data and host-data are separated and the only the meta-data is sent to the controller to be updated during a modified internal copyback operation. The host-data is not transmitted to the controller. While sending the meta-data utilizes resources of the communication link between the memory dies and the controller, it uses much fewer resources than if the host-data were also transmitted.

Metadata aware copyback for memory devices

Growing community of inventors

San Jose, CA, United States of America

Zhengang Chen