Omnivision Technologies, Inc.

Omnivisision Technology, Inc.

Zheng Yang

Hiroaki Ebihara

Tiejun Dai

Rui Wang

Andreas Suess

Eiichi Funatsu

Chao-Fang Tsai

Chun-Ming Tang

Guangbin Zhang

Donghui Wu

Xiao Xie

Yuanbao Gu

Duli Mao

Sohei Manabe

Dajiang Yang

Keiji Mabuchi

Liping Deng

Dong Yang

Taehyung Jung

Zhiyong Zhan

Ling Fu

Bowei Zhang

Olivier Bulteel

Wei Deng

Chun-Hsiang Chang

Zhenfu Tian

Wenhao Qiao

Hoon Ryu

Tongtong Yu

Chia-Ming Chen

Qi Niu

Hyunsu Yoon

Teijun Dai

Shijing Yao

A time-of-flight sensor includes an integrated circuit chip in which a voltage regulator and a load are disposed. The load includes a grouping of pixel circuits and modulation driver that is supplied power from the voltage regulator. The grouping of pixel circuits included in a pixel array disposed in the integrated circuit trip. Each one of the pixel circuits includes a photodiode configured to photogenerate charge in response to reflected modulated light, a floating diffusion configured to store a portion of charge photogenerated in the photodiode, and transfer transistor to transfer the portion of charge from the photodiode to the floating diffusion in response to a phase modulation signal generated by the modulation driver. A feedback circuit is coupled between the load and the voltage regulator and is coupled to receive a feedback signal from the feedback circuit in response to the load.

Voltage regulation for increased robustness in indirect time-of-flight sensors

A time-of-flight pixel circuit includes a photodiode configured to generate charge in response to modulated light reflected from an object. First and second transfer transistors are coupled to the photodiode. The first transfer transistor transfers a first portion of charge from the photodiode in response to a first modulation signal and the second transfer transistor transfers a second portion of charge from the photodiode in response to a second modulation signal. The second modulation signal is an inverted first modulation signal. A first floating diffusion is coupled to the first transfer transistor to receive the first portion of charge in response to a first modulation signal. Each one of a first plurality of sample and hold transistors is coupled between a respective one of a first plurality of memory nodes and the first transfer transistor.

Readout architectures for motion blur reduction in indirect time-of-flight sensors

An imaging device includes a pixel array including a 4×4 grouping of pixel circuits. The 4×4 grouping of pixel circuits includes four rows and four columns of the pixel array. A plurality of bitlines includes a first bitline, a second bitline, a third bitline, and a fourth bitline. Each one of the first, second, third, and fourth bitlines is coupled to a respective four pixel circuits in the 4×4 grouping of pixel circuits. Each one of the first, second, third, and fourth bitlines is coupled to all four of the rows and to all four of the columns of the 4×4 grouping of pixel circuits.

Color-infrared sensor with a low power binning readout mode

A pixel circuit includes a photodiode configured to photogenerate charge in response to reflected modulated light incident upon the photodiode. A first floating diffusion is configured to store a first portion of charge photogenerated in the photodiode. A first transfer transistor is configured to transfer the first portion of charge from the photodiode to the first floating diffusion in response to a first phase signal. A first storage node is configured to store the first portion of charge from the first floating diffusion. A first decoupling circuit has a first output responsive to a first input. The first input is coupled to the first floating diffusion and the first output is coupled to first storage node. A voltage swing at the first output is greater than a voltage swing at the first input.

Readout architectures for dark current reduction in indirect time-of-flight sensors

Image sensors with improved negative pump voltage settling, and circuitry for the same, are disclosed herein. In one embodiment, a power supply settling circuit includes a negative charge pump and a reference voltage generator. An output of the negative charge pump is selectively coupled to a first node of the negative pump settling circuit via a first switch, and an output of the reference voltage generator is selectively coupled to a second node of the negative pump settling circuit via a second switch. The first node is further selectively coupled to ground via a third switch, and the second node is further selectively coupled to ground via a fourth switch. The first node can additionally be coupled to a first pad, and the second node can additionally be coupled to a second pad. The pads can each be coupled to a capacitor, such as an off-chip capacitor.

Image sensors with improved negative pump voltage settling, and circuitry for the same

A time-of-flight pixel array includes photodiodes that generate charge in response to incident reflected modulated light. First transfer transistors transfer a first portion of the charge from the photodiodes in response to a first modulation signal and second transfer transistors transfer a second portion of the charge from the photodiodes in response to a second modulation signal, which is an inverted first modulation signal. First floating diffusions are coupled to the first transfer transistors. A binning transistor is coupled between one of the first floating diffusions and another one of the first floating diffusions. A first memory node is coupled to one of the first floating diffusions through a first sample and hold transistor and a second memory node is coupled to another one of the first floating diffusions through a second sample and hold transistor.

Readout architectures for binned indirect time-of-flight sensors

A time-of-flight sensor includes a pixel array of pixel circuits. A first subset of the pixel circuits is illuminated by reflected modulated light from a portion of an object. A second subset of the pixel circuits is non-illuminated by the reflected modulated light. Each pixel circuit includes a floating diffusion that stores a portion of charge photogenerated in a photodiode in response to the reflected modulated light. A transfer transistor transfers the portion of charge from the photodiode to the floating diffusion in response to modulation by a phase modulation signal. A modulation driver block generates the phase modulation signal and is coupled to a light source that emits the modulated light to the portion of the object. The modulation driver block synchronizes scanning the modulated light emitted by the light source across the object with scanning of the first subset of the pixel circuits across the pixel array.

Readout architecture for indirect time-of-flight sensing

A pixel readout circuit includes an analog to digital converter coupled to the bitline output of the pixel circuit. A switch is coupled between the bitline output of the pixel circuit and a reference voltage. The switch is pulsed on and off a first time to settle the bitline to the reference voltage prior to an autozero operation of the analog to digital converter. The switch is pulsed on and off a second time to settle the bitline to the reference voltage after the autozero operation and prior to a first analog to digital conversion. The switch is configured to be pulsed on and off a third time to settle the bitline to the reference voltage after the first analog to digital conversion operation and prior to a second analog to digital conversion operation.

Resettle timing for low power pixel readout

A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.

Differential subrange ADC for image sensor

An imaging system includes a pixel array configured to generate image charge voltage signals in response to incident light received from an external scene. An infrared illumination source is deactivated during the capture of a first image of the external scene and activated during the capture of a second image of the external scene. An array of sample and hold circuits is coupled to the pixel array. Each sample and hold circuit is coupled to a respective pixel of the pixel array and includes first and second capacitors to store first and second image charge voltage signals of the captured first and second images, respectively. A column voltage domain differential amplifier is coupled to the first and second capacitors to determine a difference between the first and second image charge voltage signals to identify an object in a foreground of the external scene.

Image sensor with in-pixel background subtraction and motion detection

An imaging device includes pixel circuits that include either image sensing photodiodes or phase detection autofocus (PDAF) photodiodes. The PDAF photodiodes are included in a first PDAF pixel circuit included in a first grouping of rows, and a second PDAF pixel circuit included in a second grouping of rows of a pixel array. Bitline pairs are coupled to respective columns of the pixel array. Each bitline pair includes a first bitline coupled to the first grouping of rows and a second bitline coupled to the second grouping of rows of respective columns of the pixel array. Multiplexers are configured to select one of respective first or second bitlines of each bitline pair. A PDAF multiplexer is coupled to a PDAF select signal and the second PDAF circuit through a respective bitline pair. The remaining multiplexers are coupled to a select signal and are coupled to remaining bitline pairs.

Bitline control supporting binning mode phase detection autofocus photodiodes

An amplifier circuit for use in an image sensor includes a common source amplifier coupled to receive an input signal representative of an image charge from a pixel cell of the image sensor. An auto-zero switch is coupled between an input of the common source amplifier and an output of the common source amplifier. A feedback capacitor is coupled to the input of the common source amplifier. An offset switch is coupled to the feedback capacitor and is further coupled to a reset voltage and an output of the amplifier circuit. The auto-zero switch and the offset switch are configured to couple the feedback capacitor to the reset voltage during a reset of the amplifier circuit. The offset switch is configured to couple the feedback capacitor to the output of the amplifier circuit after the reset of the amplifier circuit.

Column amplifier reset circuit

A subrange analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC.

Subrange ADC for image sensor

A column amplifier with a comparator for use in an image sensor includes an amplifier coupled to receive an input signal representative of an image charge from a pixel cell of the image sensor. An amplifier auto-zero switch is coupled between an input of the amplifier and an output of the amplifier. A feedback capacitor coupled to an input of the amplifier. An amplifier output switch coupled between the output of the amplifier and the feedback capacitor. A comparator includes a first input coupled the amplifier output switch. A comparator auto-zero switch is coupled between the first input of the comparator and an output of the comparator.

Column amplifier reset circuit with comparator

A multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs. The ADCs having inputs coupled to selected pixels and outputting through-silicon vias and inter-die bond pads to a third IC coupled to buffer raw image data in DRAM. A method includes capturing images with array pixel IC divided into sub-arrays each coupled to a separate, associated, ADC through inter-die bonds, scanning the sub-arrays and converting the image data to digital image data; and transferring the digital image data over inter-die bonds into buffers in DRAM.

Growing community of inventors

San Jose, CA, United States of America

Zheng Yang