Gowin Semiconductor Corporation

Zheng Wang

Tianping Wang

Jingxiang Wang

Yue Han

Qi Zhou

Yunjie Fan

Niu Li

A system and method for testing Error Correcting Code ('ECC') function of Field Programmable Gate Array (“FPGA”) on-chip block random access memory (“BRAM”) includes control modules, at least two BRAMs with ECC function and sequentially connected to form a ring, and parity bit comparison modules corresponding to each BRAM. Each parity bit comparison module is connected to its corresponding BRAM and the next adjacent BRAM. The control module is used to send data read and write test instructions to each BRAM. Each BRAM is used to read test data sequentially, write test data into next adjacent BRAM whenever the test data is read, and send the first parity bit generated during reading to the corresponding parity bit comparison module. Each parity bit comparison module is used to compare the first and second parity bits, where the second parity bit is generated during the writing of test data. The embodiments of the present invention reduce the required test stimuli and the interactions with upper computer ports, which enhances the test efficiency.

Growing community of inventors

Guangzhou, China

Zheng Wang