Imec Vzw

Unisantis Electronics Singapore Pte. Ltd.

Katholieke Universiteit Leuven, Ku Leuven R&d

Zheng Tao

Boon Teik Chan

Efrain Altamirano Sanchez

Silvia Armini

Steven Demuynck

Fujio Masuoka

Hiroki Nakamura

Nozomu Harada

Liesbeth Witters

Anabela Veloso

Clement Merckling

Min-Soo Kim

Waikin Li

Stefan Decoster

Kaidong Xu

Vasile Paraschiv

Basoene Briggs

Marc Schaekers

Arjun Singh

Safak Sayan

Soon Aik Chew

Jan Doise

Antony Premkumar Peter

Anshul Gupta

Khashayar Babaei Gavan

XiuMei Xu

Min Soo Kim

Elisabeth Camerotto

Nadia Vandenbroeck

Xiumei Xu

Gavan Khashayar

A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.

Method and structure for determining an overlay error

A method for forming an interconnection structure for a semiconductor device and an interconnection structure is disclosed. The method includes forming a conductive layer on an insulating layer and etching the conductive layer to form a first conductive line. Thereafter, a spacer is formed on a side wall of a first end portion of the first conductive line. The method further includes forming a second conductive line, parallel to the first conductive line, having a second end portion, wherein a side wall of the second end portion is arranged to abut the spacer such that the first and the second metal line are extending along the same line and separated by the spacer. A recess is formed in the second metal line, extending along a portion of the second metal line, and a second mask layer is arranged in the recess.

Interconnection structure for a semiconductor device

A method for forming an interconnection structure () for a semiconductor device is disclosed, wherein a first conductive layer is etched to form a set of third conductive lines () above a first and second conductive line (). At least one of the third conductive lines comprises a contacting portion forming a first via connection () to the second conductive line. The method further comprises forming spacers () on side walls of the set of third conductive lines, and forming, between two neighboring spacers, a via hole () extending to the underlying first conductive line. A second conductive layer is deposited, filling the via hole to form a second via connection () and forming a set of fourth conductive lines () extending between the spacers.

Method of manufacturing an interconnection structure for a semiconductor device having a spacer separating first and second conductive lines

A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

Method for forming a buried metal line in a semiconductor substrate

In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.

Contact isolation in semiconductor devices

A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

Method for filling a space in a semiconductor

A method is provided for forming a semiconductor product including providing a substrate comprising a buried power rail; forming a sacrificial plug at a contact surface on the buried power rail; applying a front-end-of-line module for forming devices in the semiconductor substrate; providing a Via, through layers applied by the front-end-module, which joins the sacrificial plug on the buried power rail; selectively removing the sacrificial plug thereby obtaining a cavity above the buried power rail; filling the cavity with a metal to electrically connect the devices with the buried power rail, wherein the sacrificial plug is formed such that the contact surface area is larger than an area of a cross-section of the Via parallel with the contact surface.

Buried power rail contact formation

A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.

Method of forming a mask layer

The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

Method of fabricating stacked semiconductor device

A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

Method for producing a pillar structure in a semiconductor layer

In an SRAM cell circuit, an N+ layerand a P+ layer, which are present between first gate connection W layersandconnecting to gate TiN layersandin plan view, which connect to the bottom portions of Si pillarsand, and which extend in the horizontal direction, connect through a second gate connection W layerto a first gate connection W layer, which connects to the gate TiN layersandand extend in the horizontal direction. The second gate connection W layerhas a bottom portion within the first gate connection W layer, and has an upper surface positioned lower than the upper surfaces of the gate TiN layerstoand the first gate connection W layersto

Pillar-shaped semiconductor device and method for producing the same

A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

Method for forming horizontal nanowires and devices manufactured thereof

A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. On the main surface, a first pair of features are formed that protrude perpendicularly from the main surface. The features have elongated sidewalls and a top surface, are parallel to one another, are separated by a gap having a width sand a bottom area, and have a width wand a height h. At least the main surface of the substrate and the first pair of features are brought in contact with a liquid, suitable for making a contact angle of less than 90&#xb0; with the material of the elongated sidewalls and subsequently the substrate is dried.

Method of forming micro-pipes on a substrate and a structure formed thereof

A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

Method of forming internal spacer for nanowires

A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method includes epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

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Heverlee, Belgium

Zheng Tao