Intel Corporation

Zheng Guo

Eric A Karl

Clifford L Ong

Smita Shridharan

George Shchupak

Tali Kosinovsky

Mark T Bohr

Gunjan H Pandya

Uddalak Bhattacharya

Pramod Kolar

Ram K Krishnamurthy

Stefan Rusu

Sanu K Mathew

Dinesh Somasekhar

Charles Henry Wallace

Mauro J Kobrinsky

Leonard P Guler

Shem Ogadhoh

Gururaj Shamanna

Clifford J Engel

Xiaofei Wang

Eirc A Karl

Gordon Carskadon

Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.

Backside electrical contact for PMOS epitaxial voltage supply

Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Internal node jumper for memory bit cells

Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Uniform layouts for SRAM and register file bit cells

Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.

Multi-bit read-only memory device

An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.

Row based memory write assist and active sleep bias

Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Apparatus for adaptive write assist for memory

In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Dual-port static random access memory (SRAM)

A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bitsw-w of Y to generate bitsw-w of product Z, and addition of bitsw-w of modulus M to bitsw-w of product Z if the least-significant bit of product Z is 1. Multiplying the least-significant bit of X and bitsw-w of Y may occur at least partially contemporaneously with multiplying the least-significant bit of X and the least-significant w bits of Y, determining if the least-significant bit of product Z is 1, and adding the least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1.

Modular multiplication acceleration circuit and method for data encryption/decryption

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Hillsboro, OR, United States of America

Zheng Guo