Symetrix Corporation

Matsushita Electric Industrial Co., Ltd.

Matushita Electric Industrial Co., Ltd.

Zheng Chen

Carlos Alberto Paz De Araujo

Larry D McMillan

Vikram Joshi

Myoungho Lim

Yasuhiro Shimada

Yoshihisa Kato

Jolanta Bozena Celinska

Tatsuo Otsuki

A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile and provide for each of the memory cells to be randomly accessed.

1T1R resistive memory array with chained structure

A device and method of reading a ferroelectric memory, including providing a ferroelectric memory including a ferroelectric memory cell, a charge integrator, and a bit line connecting the ferroelectric memory cell and the charge integrator. Pulses are applied to the ferroelectric memory cell, where each of the pulses are of a value lower than that which will destroy data stored in the memory cell. Output voltage values from the ferroelectric memory cell are accumulated by the charge integrator in response to each pulse. The output of the charge integrator may be read to determine whether the datum value stored in the memory cell is a logic high or low value. In one embodiment, the output of the charge integrator is read at a predetermined time after starting the pulses.

Non-destructive readout of ferroelectric memories

A pyrometer cell comprises a first ferroelectric capacitor, a second ferroelectric capacitor, and a difference circuit for determining the difference between the polarization charge, voltage, or current between the first and second ferroelectric capacitors. The cell is pulsed a plurality of times and an integrator circuit connected to the difference circuit provides an enhanced output signal representative of the integrated difference. An infrared imager is formed by an array of the pyrometer cells, with one ferroelectric capacitor in each cell exposed to an infrared source and the other ferroelectric capacitor not exposed to the infrared source.

Infrared sensor and imager with differential ferroelectric cells

A non-volatile SRAM memory comprising a plurality of memory cells, each memory cell including a SRAM memory cell portion and a ferroelectric memory cell portion including a ferroelectric element, the ferroelectric memory cell portion including a switch system for permitting the ferroelectric element to be isolated from the ferroelectric elements in all other memory cells.

Non-volatile ferroelectric SRAM

A ferroelectric memoryincludes a group of memory cells (), each cell having a ferroelectric memory element (etc.), a drive line (etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (etc.) between the memory cells and the bit line, a set switch (etc.) connected between the drive line and the memory cells, and a reset switch (etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.

Ferroelectric memory and method of operating same

A ferroelectric non-volatile memory comprising: a plurality of memory cells each containing a ferroelectric FET, each of said ferroelectric FETs having a source, a drain, a substrate, and a gate. The FETs are arranged in an array comprising a plurality of rows and a plurality of columns. There are a plurality of row select lines, each associated with one of the rows of said ferroelectric FETs, and a plurality of column select lines, each associated with one of the columns of ferroelectric FETs. Each of the sources is directly electrically connected to its associated row select line, and each of the drains is directly electrically connected to its associated column select line. The source and substrate of each FET are also directly electrically connected. A memory cell is read by connecting its row select line to ground, and its column select line to a small voltage. All the gates, and the row select lines of non-selected cells are open or connected to a high resistance source. Thus, the current in the selected column select line and row select line is a measure of the state of the selected cell. Each FET is fabricated using a self-aligned process so that no portion of a source/drain underlies the gate.

A ferroelectric non-volatile memory comprising: a plurality of memory cells, each containing an FeFET and a MOSFET, each of said FeFETs having a source, a drain, a substrate, and a gate, and each MOSFET having a pair of source/drains and a gate. The cells are arranged in an array comprising a plurality of rows and a plurality of columns. A gate line and a bit line are associated with each column, and a word line, a drain line, and a substrate line are associated with each row. One source/drain of each MOSFET is connected to its corresponding gate line; the other source/drain is connected to the gate of the FeFET in the cell. The gate of the MOSFET is connected to its corresponding word line which provides a write and erase enable signal. The drain of the FeFET is connected to its corresponding drain line, and the source of the FeFET is connected to its corresponding bit line. The substrate of each FeFET is connected to its corresponding substrate line. A read MOSFET is connected between a drain input and the drain line associated with each row. The gate of the read MOSFET is connected to an input for the read enable signal.

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Colorado Springs, CO, United States of America

Zheng Chen