Lattice Semiconductor Corporation

Zheng Chen

John Schadt

Wei Han

Fulong Zhang

Larry Fenstermaker

William B Andrews

Barry Britton

Warren Juenemann

Rohith Sood

Eric Lee

Phillip Johnson

Loren McLaury

Richard G Stuby, Jr

Ming Hui Ding

Anthony K Myers

Chien Kuang Chen

David A Rhein

Warren L Ziegenfus

Fabiano Fontana

Hemanshu T Vernenker

Allen White

Mou C Lin

Richard Booth

Christopher Hume

Mose Wahlstrom

Glen Edward Offord

James F Hoff

Gregory S Cartney

Kanad Chakraborty

Nhon Nguyen

Jamie Freed

Cort D Lansenderfer

Ravikumar Charath

Ju-Yuan D Yang

Jie Qin

Don McCarley

Shankar Durgamahanthi

Dan Ratchen

In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.

Highly secure and extensive scan testing of integrated circuits

In one embodiment, a programmable logic device includes a memory and an input/output (I/O) interface adapted to enter a variable response mode responsive to an assertion of a control signal. The I/O interface is operable in the variable response mode to respond to a read command from an external device by retrieving data from the memory and to shift dummy data to the external device until an internal data ready signal is asserted.

Variable response mode for synchronous data read

A programmable logic device (PLD) is provided that includes: a configuration memory including a plurality of memory cells arranged according to rows and columns, wherein a subset of the rows are RAM rows, and wherein a subset of the columns in each RAM row are RAM columns and at least one column in each RAM row is a flag bit column, the memory cells corresponding to the flag bit column and RAM rows operable to store flag bit signals; a soft error detection (SED) circuit operable to read the configuration memory to derive a checksum; a logic circuit to determine if a RAM row is being read by the SED circuit that includes an asserted flag bit; and a blocking circuit that provides a known logical value to the SED circuit responsive to the logic circuit to block readback of the memory cells corresponding to the RAM rows and RAM columns.

Blocking memory readback in a programmable logic device

Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a programmable logic device (PLD) includes a plurality of static random access memory (SRAM) cells adapted to configure the PLD for an intended use. A pair of bitlines are connected to the SRAM cells. At least one of the SRAM cells is adapted to provide data signals to the bitlines in response to a wordline signal received by the one of the SRAM cells during a read operation. A sense amplifier is connected to the bitlines and adapted to detect a data value from the data signals in response to a trigger signal received by the sense amplifier during the read operation. Logic is adapted to delay the trigger signal relative to the wordline signal to permit the data signals to settle before the sense amplifier detects the data value.

Triggered sense amplifier

In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8&#xd7;1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4&#xd7;1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4&#xd7;1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

Low-power configurable delay element

In one embodiment of the invention, a programmable logic device, such as an FPGA, has programmable I/O circuits that can be programmed into any one of a number of different operating modes before configuration is completed. As such, the same set of I/O circuits and corresponding I/O pads can be used to configure the device using different configuration interfaces having different interface signaling requirements. Such a device may be able to be implemented using fewer I/O pads than conventional devices that employ a different set of I/O pads for each different type of configuration interface supported by the device.

Pre-configuration programmability of I/O circuitry

In one embodiment, a programmable logic device such as an FPGA includes a programmable fabric adapted to operate normally and in a sleep mode, and a general purpose input/output port (I/O). The I/O port is adapted to function in conventional fashion during normal operation of the programmable fabric and as a wakeup control port during the sleep mode.

Programmable logic device wakeup using a general purpose input/output port

Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.

Bitline floating circuit for memory power reduction

A programmable logic device (PLD) is disclosed that includes a non-volatile memory; a shadow register; and a data shift register (DSR) configurable to receive control information from an external programming tool, wherein the DSR is configured to shift the control information into the shadow register if the PLD is in a first programming mode, the PLD being configurable to operate in the first programming mode using the control information stored in the shadow register without the control information being stored in the non-volatile memory.

Safe programming of key information into non-volatile memory for a programmable logic device

Low-power, glitch-less, configurable delay element

An integrated circuit includes, in accordance with an embodiment of the present invention, a data port, a system bus for transferring information to and from the data port, and a plurality of SERDES channels. A plurality of registers associated with the plurality of SERDES channels may be written to via the system bus on an individual, group, or global basis to provide communication settings for the SERDES channels.

Multiple communication channel configuration systems and methods

In one embodiment of the invention, a method of generating a compressed configuration bitstream for a programmable logic device comprises encoding the most-prevalent data word within the configuration data of the bitstream into a codeword of a first type; encoding a set of more-prevalent data words within the configuration data into codewords of a second type; and including in the compressed bitstream at least some of the data words that are members of the set of more-prevalent data words. The included data words, when received by the programmable logic device, are adapted to be identified by the device as members of the set of more-prevalent data words. The included data words are stored for selection by the device when a codeword of the second type representing an included data word is received by the device.

Efficient bitstream compression

In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits

In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.

Dynamic delay or advance adjustment of oscillating signal phase

According to one embodiment of the invention, a method of generating a compressed configuration bitstream for a programmable logic device comprises encoding the most-prevalent data word within the configuration data of the bitstream into a first type of code word; encoding a set of more-prevalent data words within the configuration data into a second type of codeword; and identifying in the compressed bitstream at least some of the data words that are members of the set of more-prevalent data words.

Growing community of inventors

Upper Macungie, PA, United States of America

Zheng Chen