Csmc Technologies Fab2 Co., Ltd.

China Resources Microelectronics (chongqing) Co., Ltd.

Csmc Technologies Fab1 Co., Ltd.

Zheng Bian

Dong Fang

Kui Xiao

Jinjie Hu

The present application relates to a semiconductor device, comprising a substrate, with a body region being formed on the substrate, and a well region being formed in the body region; and further comprising trenches penetrating through the well region and the body region and extending to the substrate, wherein a first polysilicon body and a second polysilicon body, which are isolated from each other, are respectively formed at the bottom and the top of each trench to form a split gate structure, the trenches are filled with an inter-layer dielectric layer, a conductive plug penetrating through the inter-layer dielectric layer and extending into the first polysilicon body is formed in each trench, the conductive plug is isolated from the second polysilicon body by means of the inter-layer dielectric layer, the conductive plug is connected to a source electrode, and the second polysilicon body is connected to a gate electrode.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device comprises a drift region (), a body region (), a first doped region () and a second doped region ()); a first trench penetrates the first doped region (), the body region () extends into the drift region (); an extension region () having an opposite conductivity type to the drift region () and surrounding the bottom wall of the first trench; where the first trench is filled with a first conductive structure () and a second conductive structure (); a dielectric layer () formed between the second conductive structure () and the inner wall of the first trench, as well as between the first conductive structure () and the inner wall of the first trench; a second trench penetrating the first doped region () and the body region (), and a dielectric layer () located between the third conductive structure () and the second trench ().

Semiconductor device and preparation method thereof

A preparation method for semiconductor device, comprising: forming a body region () in the drift region (), forming a first doped region () and a second doped region () in the body region (); forming a first trench () penetrating the first doped region () and the body region () and extending to the drift region (); forming an extension region () with a conductivity type opposite to that of the drift region () and surrounding the bottom wall of the first trench (); filling the first trench () with a dielectric layer () formed on the sidewall of the trench, a first conductive structure () located at the bottom of the trench and a second conductive structure () located at the top of the trench; forming a second trench () penetrating the body region () and extending into the drift region (); filling the second trench () with a third conductive structure () and a dielectric layer () formed on the inner wall of the trench. The second conductive structure () is electrically connected with the gate, and the first doped region (), the second doped region (), and the third conductive structure () are electrically connected with the first electrode ().

Semiconductor device and preparation method therefor

A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.

VDMOS device and manufacturing method therefor

A VDMOS device and a manufacturing method therefor. The manufacturing method comprises: forming a groove in a semiconductor substrate, the groove comprising a first groove area, a second groove area, a third groove area, a fourth groove area and a fifth groove area; successively forming a first insulation layer, a first polycrystalline silicon layer and a second insulation layer on the semiconductor substrate; removing some of the second insulation layer until the first polycrystalline silicon layer is exposed; removing some of the first polycrystalline silicon layer, the remaining first polycrystalline silicon layer forming a first electrode; forming a third insulation layer on the semiconductor substrate, removing some of the third insulation layer, the second insulation layer and the first insulation layer, so that the top of the first polycrystalline silicon layer is higher than the top of the first insulation layer and the second insulation layer; and successively forming a gate oxide layer and a second polycrystalline silicon layer on the semiconductor substrate, and removing some of the second polycrystalline silicon layer, exposing the gate oxide layer located on the surface of the semiconductor substrate and the top of the second insulation layer, the remaining second polycrystalline silicon layer forming a second electrode.

A trench gate lead-out structure comprises a substrate (), a trench formed in the surface of the substrate () and a first dielectric layer () on the substrate (), and also comprises a polysilicon gate () at the inner surface of the trench. The trench is partially filled by the polysilicon gate (), so that a recess exists in the trench above the polysilicon gate (). A second dielectric layer () is filled in the recess. The trench gate lead-out structure also comprises a metal plug (). The metal plug () downwards penetrates through the first dielectric layer () and then is inserted between the second dielectric layer () and the polysilicon gate (), and accordingly is connected to the polysilicon gate ().

Trench gate lead-out structure and manufacturing method therefor

A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.

Semiconductor device having electro-static discharge protection structure

A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (), a trench on the surface of the substrate (), an insulating spacer () on the substrate (), a gate oxide layer () on the inner surface of the trench, and a polysilicon gate () on the gate oxide layer (). The insulating spacer () abuts against the trench by means of a slope structure () of the insulating spacer; the polysilicon gate () extends onto the insulating spacer () along the slope structure () in the trench; the insulating spacer () comprises a polysilicon gate pull-up area () that is concave downwards with respect to other parts of the insulating spacer (); the polysilicon gate () extending out of the trench is rested on the polysilicon gate pull-up area ().

Trench gate structure and manufacturing method therefor

A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench () formed on a substrate (); the trench () comprises a bottom surface and two side surfaces extending from the bottom surface; the trench () is formed on the substrate () with a preset angle of non-90&#xb0; formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.

Test pattern for trench poly over-etched step and formation method thereof

A trench-type DMOS device includes a substrate as a public drain region, an active region and a voltage-dividing ring formed on the substrate, and a first dielectric layer formed on the substrate. Multiple trenches are located on the first dielectric layer, and the trenches extend from the surface of the first dielectric layer into the interior of the substrate. The trenches comprise at least one first trench distributed in the active region and a second trench outside the active region. A gate oxide layer is formed in the trench and polycrystalline silicon is filled to form a gate. The active region further comprises a source electrode region and a P-type heavily doped region under the source electrode region. A second dielectric layer covers the first dielectric layer and the multiple trenches. A metal layer covers the second dielectric layer to form a first electrode region and a second electrode region.

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Jiangsu, China

Zheng Bian