Intermolecular, Inc.

Kabushiki Kaisha Toshiba

Globalfoundries Inc.

Sandisk 3D LLC

Apple Inc.

Zhendong Hong

Olov B Karlsson

Usha Raghuram

Amol Ramesh Joshi

Ashish Bodke

Takeshi Yamaguchi

Imran Hashim

Tim Minvielle

Vidyut Gopal

Hieu T Pham

Randall Higuchi

Bei Li

Paul Raymond Besser

Hoon Sik Kim

Kisik Choi

Jinping Liu

John S Foster

Sean Barstow

Jingang Su

Salil Mujumdar

Divya Pisharoty

Susie Tzeng

Bin Yang

Wei Hsin Yao

Dipankar Pramanik

Indranil De

Jeremy Cheng

Xunyuan Zhang

Chi-I Lang

Marc Albrecht

Anh Duong

Mark V Raymond

Hong Sheng Yang

Pierre-Yves Emelie

Vivian Ryan

Tobias Jung

Edwin Adhiprakasha

Duane M Petrovich

Karthik Ramani

Charlene Chen

Mohammad Tofighi

Ho Yin Owen Fong

Dan Wang

Ashley Lacey

Meng Cao

Jiulong Shan

Shuo Han

A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated by a backlight unit that includes an array of light-emitting diodes (LEDs). The backlight unit may determine the type of content in the image data. The backlight unit may decide to prioritize either mitigating halo or mitigating clipping based on the type of content. The determination of the type of content in the image data may be used to determine the brightness values for the LEDs in the LED array. If the content is determined to be a first type of content, at least one given LED in the LED array may have a different brightness value than if the content is determined to be a second, different type of content. Classifying content in the image data may be useful in optimizing visible artifacts such as visible halo and clipping.

Using content type to select brightness in direct-lit backlight units

An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Gate structures for transistor devices for CMOS applications and products

Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu&#x2014;Mn seed layer between the Ta&#x2014;Ti and copper.

Combinatorial screening of metallic diffusion barriers

Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Atomic layer deposition of metal oxides for memory applications

One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Methods of forming gate structures for transistor devices for CMOS applications

Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.

Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach

Apparatuses and methods for high-deposition-rate sputtering for depositing layers onto a substrate are disclosed. The apparatuses generally comprise a process chamber; one or more sputtering sources disposed within the process chamber, wherein each sputtering source comprises a sputtering target; a substrate support disposed within the process chamber; a shield positioned between the sputtering sources and the substrate, the shield comprising an aperture positioned under each sputtering source; and a transport system connected to the substrate support capable of positioning the substrate such that one of a plurality of site-isolated regions on the substrate can be exposed to sputtered material through the aperture positioned under each of the sputtering sources; wherein the spacing between the sputtering target and the substrate is less than 100 mm. The apparatus enables high deposition rate sputtering onto site-isolated regions on the substrate.

Combinatorial processing using high deposition rate sputtering

Substrate processing including correction for deposition location is described, including a combinatorial processing chamber that incorporates the correction. The combinatorial processing chamber can be used to process multiple regions of a substrate using different processing parameters on different regions. For example, one region can have one material deposited on it and another region can have a different material deposited on it, although other combinations and variations are possible. The combinatorial processing chamber uses a rotating and revolving substrate pedestal to be able to deposit on all locations or positions on a substrate. The combinatorial processing chamber uses a correction factor that accounts for variations in alignment and/or configuration of the processing chamber so that the actual location of deposition of a region is approximately the same as a desired location of deposition.

Substrate processing including correction for deposition location

Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Circular transmission line methods compatible with combinatorial processing of semiconductors

Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction

Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices.

High productivity combinatorial workflow for photoresist strip applications

Growing community of inventors

San Jose, CA, United States of America

Zhendong Hong