Marvell Asia Pte., Ltd.

Marvell International Limited

Marvellworld Trade Ltd.

Zhendong Guo

Hui Zhao

Jun Ming

Min She

Fei Lu

Fang Lv

Qikun Xue

Banglong Qian

Peng Liu

Yuxiang Sun

Transceiver circuitry for coupling a functional circuit to a transmission medium includes a transmit path for coupling between the functional circuit and the transmission medium, a receive path for coupling between the transmission medium and the functional circuit, and clock generation circuitry coupled to at least one of the transmit path and the receive path. The clock generation circuitry includes an oscillator having transconductance circuitry, a capacitance element coupled in parallel with the transconductance circuitry, a plurality of inductors coupled in parallel with the transconductance circuitry and the capacitance element, and with each other, and a current source coupled to the plurality of inductors. The capacitance element may be variable. An even number of inductors are arranged so that half of the inductors generate magnetic flux in a first direction, and half of the inductors generate magnetic flux in a second direction opposite to the first direction.

Oscillator for high-speed serial device

An integrated circuit device includes functional circuitry, and serializer/deserializer circuitry for serial communication with the functional circuitry. The serializer/deserializer circuitry includes phase interpolator circuitry for interpolating phases of a clock signal of the integrated circuit device. The phase interpolator circuitry includes a phase shift register having storage locations configured to represent the phases of the clock signal, and phase rotation control circuitry configured to decode a phase code signal to determine a shifting direction for phase selections in storage locations of the phase shift register. The phase rotation control circuitry may be configured to determine the shifting direction based on only the most significant bit and the second most significant bit of the phase code signal. The phase interpolator circuitry may further include weight decoder circuitry configured to derive, from the phase code signal, interpolation weights to control combination of selected phases of the clock signal.

Shift-register-based clock phase interpolator

Receiver circuitry to convert a pulse-width-modulated (PWM) signal into a digital data signal includes analog-to-digital converter circuitry that converts the PWM signal into an intermediate signal, a timing generator that derives control signals from the intermediate signal, analog charge storage circuitry that is charged and discharged according to the control signals, and circuitry that derives a digital output signal from an analog waveform output by the charge storage circuitry. The charge storage circuitry includes a capacitance and a current-limiting element, one of which is variable to control a time constant of the charge storage circuitry for calibration to a data rate of the PWM signal. A control signal may be single-ended and compared to a threshold, or may be differential with the legs compared to each other. The output is derived on a falling clock edge, and maintained until a subsequent falling clock edge.

Analog-based pulse-width modulation receiver

Aspects of the disclosure provide an integrated circuit (IC) chip with an on-chip transformer. The on-chip transformer includes a primary inductor and a secondary inductor. The primary inductor is configured to have a first-primary coil portion formed of a first patterned metal trace disposed in a first metal layer and a second-primary coil portion formed of a second patterned metal trace disposed in a second metal layer. The secondary inductor is configured to have a first-secondary coil portion formed of a third patterned metal trace that interleaves with the first patterned metal trace in the first metal layer and a second-secondary coil portion formed of a fourth patterned metal trace that interleaves with the second patterned metal trace in the second metal layer.

On-chip inductors

Linearity of a PAM-4 voltage-mode driver is improved using current compensation. The driver receives a first input data signal having a first logic level and a second input data signal having a second logic level. In an additive current mode, when the first logic level matches the second logic level, the driver uses switch circuitry to form an auxiliary current path through which supplementary current (I_Supplementary) flows from a voltage regulator. In a primary current mode, when the first logic level does not match the second logic level, the driver uses the switch circuitry to break the auxiliary current path, thereby preventing the supplementary current (I_Supplementary) from flowing from the voltage regulator.

PAM-4 voltage-mode driver with stabilized output

Aspects of the disclosure provide a sense amplifier that includes a first amplifying circuit, a second amplifying circuit, a coupling circuit and a detection circuit. The first amplifying circuit is configured to receive an input signal that carries digital values and amplify the input signal to generate a first output. The coupling circuit is configured to combine the input signal with an offset signal to form a combined signal. The offset signal is used to cancel an offset of the first amplifying circuit. The second amplifying circuit is configured to receive the combined signal of the input signal and the offset signal and amplify the combined signal to generate a second output. The first output and the second output are combined to form a combined output. The detection circuit is configured to detect the digital values based on the combined output.

Sense amplifier

An inverter cell for a ring oscillator. The inverter cell includes a first transistor, a second transistor, a first resistor, a second resistor, and a capacitor. A voltage input terminal is connected to gates of the first transistor and the second transistor. A voltage output terminal is connected drains of the first transistor and the second transistor. The first resistor is connected to the source of the first transistor and a first voltage potential. The second resistor is connected to the source of the second transistor and a second voltage potential. The capacitor has a first end directly connected to the source of the first transistor and the first end of the first resistor and a second end directly connected to the source of the second transistor and the first end of the second resistor.

Inverter cell for a ring oscillator

Disclosed is an inverter cell design comprising first and second transistors and first and second resistors. In disclosed embodiments, the first resistor is connected to a source of the first transistor and the second resistor is connected to a source of the second transistor. The first and second resistors are configured for connection to respective first and second voltage potentials. The inverter cells may be configured in a ring oscillator. A crystal oscillator may comprise an inverter cell according to the present disclosure.

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San Jose, CA, United States of America

Zhendong Guo