Boe Technology Group Co., Ltd.

Beijing Tsingmicro Intelligent Technology Co., Ltd.

Chengdu Boe Optoelectronics Technology Co., Ltd.

International Business Machines Corporation

Beijing Boe Display Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Beijing Jingdong Shangke Information Technology Co., Ltd.

Beijing Jingdong Century Trading Co., Ltd.

Beijing S-tech Technology Co. Ltd

Telefonaktiebolaget Lm Ericsson (publ)

Beijing Xiaomi Mobile Software Co., Ltd.

Beijing Didi Infinity Technology and Development Co., Ltd.

Beijing Welion New Energy Technology Co., Ltd

Zhen Zhang

Chenyang Zhang

Fuqiang Li

Yunping Di

Peng Ouyang

Binbin Tong

Xue Dong

Jian Wang

Yue Wang

Ce Ning

Zhenyu Zhang

Lizhong Wang

Guangcai Yuan

Zheng Fang

Jiahui Han

Chengfu Xu

Lei Wang

Xiaoliang Ding

Rui Huang

Zhanfeng Cao

Jianbo Xian

Jing Li

Tingliang Liu

Yuzhen Guo

Chunping Long

Ke Fei Wang

Wei Yang

Xianqin Meng

Pengxia Liang

Yunke Qin

Zhiwei Liang

Jian Min Jiang

Liping Lei

Muxin Di

Xinwei Wu

Qi Yang

Yuqing Yang

Tianmin Zhou

Yingchao Zhou

Lubin Shi

Wenrui Li

Lizhen Zhang

Yue Wei

Ning Zhao

Peng Jia

Weiting Peng

Mingxing Wang

Chongyang Wang

Zi Ming Huang

Huigen Yu

Qiuli Wang

Zexiang Huang

Kehua Sheng

Quancheng Rao

Taixu Jiang

Xiawei Yun

Feihu Zhou

Yawei Wang

Wanqing Liu

Kejia Zhu

Junbao Hu

Xudong An

Shengbin Wang

A processor obtains a pair including a question and an answer in natural language; determines at least one entity in the question and an entity type of each of the at least one entity consistent with the schema of a knowledge graph (KG); identifies a subset of candidate query templates based on the entity type of each of the at least one entity, wherein the candidate query templates are generated based on the schema of the KG; composes a set of queries by populating the at least one entity into each of the subset of candidate query templates; executes the set of queries on the KG to generate respective answers; identifies a first answer from the respective answers that is matching with the answer in the pair; and determines a candidate query template, from the subset of candidate query templates, corresponding to the first answer as a query template.

Generation of query templates for knowledge-graph based question answering system

Disclosed are a thin film transistor and a manufacturing method therefor, a displaying base plate and a displaying apparatus. The thin film transistor includes an active layer, a first insulating layer and a gate layer which are disposed in stack, wherein the active layer includes a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area includes a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction; the gate layer includes a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area; and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area.

Displaying base plate and manufacturing method thereof, and displaying device

An OLED display device, including an array substrate, wherein the array substrate including: a display area and a peripheral area, wherein a common electrode is provided in the display area and an electrode bus is provided adjacent to the display area in the peripheral area; a first electrode pad provided on a side of the peripheral area distal to the display area, wherein the first electrode pad is a cathode pad; a first conductive portion connected to the first electrode pad and the common electrode; a second electrode pad provided on a side of the peripheral area distal to the display area, wherein the second electrode pad is an anode pad; and a second conductive portion connected to the second electrode pad and extending, in a direction opposite to the first conductive portion, to be connected to the electrode bus.

Array substrate and display device

Disclosed are a display substrate and a display apparatus, the display substrate includes a display region and a non-display region, the display region is provided with a pixel circuit and a light emitting unit; each pixel circuit is connected with K light emitting devices emitting light of a same color; each pixel circuit includes a current control sub-circuit and a light emitting selection sub-circuit; the current control sub-circuit is configured to provide a drive current to a first node under control of a reset signal terminal, an initial signal terminal, a scan signal terminal, a data signal terminal, a light emitting control terminal, and a first power supply terminal; the light emitting selection sub-circuit is configured to sequentially provide a signal of the first node to the K light emitting devices emitting light of the same color under control of K light emitting selection signal terminals.

Display substrate and display apparatus

An array substrate and a display panel. The array substrate includes: a base substrate; a gate line and a data line on the base substrate, the gate line intersect the data line to define a pixel region; a metal oxide thin film transistor is arranged in the pixel region, the metal oxide thin film transistor includes a metal oxide semiconductor layer; the metal oxide semiconductor layer includes a first part and a second part; the first part and the data line are connected through a first via hole; the first part is in a stripe shape; a first included angle is between extension directions of the first part and the data line; an orthographic projection of the second part overlap with an orthographic projection of the gate line on the base substrate and do not overlap with an orthographic projection of the data line on the base substrate.

Array substrate and display panel

A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

Disclosed in embodiments of the present application are an information presentation method and device. One specific embodiment of a system comprises: receiving a collocation request for performing clothing collocation on target clothing, the collocation request comprising a target clothing image; performing feature extraction on the target clothing image to obtain a feature vector of the target clothing image; and selecting, from a preset clothing information set on the basis of the feature vector of the target clothing image, a clothing image having a feature vector matching the feature vector of the target clothing image to form at least one group of clothing collocation images together with the target clothing image, wherein the clothing information set comprises clothing images and feature vectors of the clothing images. The embodiment improves clothing collocation effects.

Method and apparatus for presenting information

A sensor device, an electronic apparatus and a method for reducing signal noise are provided. The sensor device includes a first detection region and a second detection region. The first detection region includes at least one detector unit, the detector unit includes a first detection electrode and a second detection electrode opposed to each other and a first insulating layer, the first detection electrode is electrically insulated from the second detection electrode by the first insulating layer, the second detection region includes at least one detector unit, the sensor unit includes a first sensor electrode, a second sensor electrode and a first photosensitive layer, and the first photosensitive layer is electrically connected to the first sensor electrode and the second sensor electrode.

Sensor device, electronic apparatus, and method for reducing signal noise

Provided are a memory coupled compiling method and system of a reconfigurable chip. The memory coupled compiling method includes: acquiring a cycle number of a data flow graph (DFG); acquiring a linear transformation vector of the cycle number through a mapping time difference; determining whether a linear array of the linear transformation vector is acquired by a heuristic algorithm; acquiring a memory mapping result through a current DFG or acquiring a cycle number of the current DFG until the linear array is acquired, depending on the determination result.

Memory coupled compiling method and system of reconfigurable chip

A light-emitting diode (LED) chip includes a plurality of epitaxial structures, at least one first electrode, and a plurality of second electrodes. Any two adjacent epitaxial structures of the plurality of epitaxial structures have a gap therebetween. Each epitaxial structure includes a first semiconductor pattern, a light-emitting pattern and a second semiconductor pattern stacked in sequence. First semiconductor patterns in at least two of the plurality of epitaxial structures are connected to each other to form a first semiconductor layer. A first electrode is electrically connected to the first semiconductor layer. Each second electrode is electrically connected to the second semiconductor pattern in at least one of the plurality of epitaxial structures.

Light-emitting diode chip having a gap between epitaxial structures and method for manufacturing the same, and display device

A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.

Mapping method and mapping device for reconfigurable array

An instruction scheduling method and an instruction scheduling system for a reconfigurable array processor. The method includes: determining whether a fan-out of a vertex in a data flow graph (DFG) is less than an actual interconnection number of a processing unit in a reconfigurable array; establishing a corresponding relationship between the vertex and a correlation operator of the processing unit; introducing a register to a directed edge, acquiring a retiming value of each vertex; arranging instructions in such a manner that retiming values of the instruction vertexes are in ascending order, and acquiring transmission time and scheduling order of the instructions; folding the DFG, placing an instruction to an instruction vertex; inserting a register and acquiring a current DFG; and acquiring a common maximum subset of the current DFG and the reconfigurable array by a maximum clique algorithm, and distributing the instructions.

Instruction scheduling method and system for reconfigurable array processor

Provided are a display panel, a manufacturing method therefor, and a display device. The display panel comprises a hole in a display region and comprises: a substrate; a drive circuit layer comprising a thin film transistor; a wire, connected to the thin film transistor; one or more isolation members surrounding the hole, disposed on the side of the drive circuit layer, and located between the wire and the hole, at least one isolation member comprising a first and a second isolation layer, and an orthographic projection of a surface of the first isolation layer away from the substrate is inside that of the second isolation layer on the substrate; a planarization layer, on the side of the drive circuit layer and covering the wire; and an anode, on the side of the planarization layer and connected to the wire by a via penetrating the planarization layer.

Display panel, manufacturing method therefor, and display device

Sport utility vehicle

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Zhen Zhang