International Business Machines Corporation

Boe Technology Group Co., Ltd.

Globalfoundries Inc.

Chengdu Boe Optoelectronics Technology Co., Ltd.

Hefei Boe Optoelectronics Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Beijing Didi Infinity Technology and Development Co., Ltd.

Beihang University

Boe Technology Groupco., Ltd.

Qualcomm Incorporated

Telefonaktiebolaget Lm Ericsson (publ)

Tencent Technology (shenzhen) Company Limited

Tsinghua University

Beijing Xiaomi Mobile Software Co., Ltd.

University of Illinois

Zhen Zhang

Fei Liu

Zhengwen O Li

Christian Lavoie

Qing Cao

Kangguo Cheng

Bin Yang

Ahmet Serkan Ozcan

Dechao Guo

Marwan H Khater

Xinwei Wu

Michael A Guillorn

Paul Michael Solomon

Yu Zhu

Wei Zhang

Yuqing Yang

Jonguk Kwak

Bo Gao

Tak H Ning

Tingliang Liu

Ying Liu

Zhi Hu Wang

Xin Zhou

Fei Fei Li

Bin Jia

Chang Jie Guo

Kejia Wang

Devendra K Sadana

Yue Wang

Wei Sun

Zhong Su

Robert H Dennard

Cheng Fang Wang

Eric Andrew Joseph

Jin Cai

Stephen Mark Rossnagel

Xianjie Shao

Junjie Zhao

Yuan-Chi Chang

Yanning Sun

Honggang Gu

Min Wang

Xiaoyan Shao

Wei Deng

Ping Xiao

Lipyeow Lim

Jie Song

Ji Dong Li

Guo Qiang Li

Juntao Li

Ghavam G Shahidi

Chun-chen Yeh

Tom Chin

Wilfried Haensch

Ke Dai

Kuo-Chun Lee

Josephine B Chang

Keith Kwong Hon Wong

Davood Shahrjerdi

Jeehwan Kim

Katherine Lynn Saenger

Yang Zhang

Chengwen Pei

Michael Patrick Chudzik

Kenneth Parker Rodbell

Joel Pereira De Souza

Shailesh Maheshwari

John Michael Cotte

Kisik Choi

Cheng Li

Kuen-Ting Shiu

Jun Yan

Damon B Farmer

Unoh Kwon

Peng Li

Qiqing Christine Ouyang

Sivaramakrishna Veerepalli

Ralph Akram Gholmieh

Wei Peng Huang

Harold John Hovel

Daniel Amerga

Mahadevaiyer Krishnan

Parthasarathy Krishnamoorthy

Sheng Wang

Sunfei Fang

Hui Fu Jiang

Frank G Kuechenmeister

Wen Sun

Michael Zhouying Su

Benjamin L Fletcher

Xiang Wang

Laura Louise Kosbar

Jianting Wang

Ming Cai

Jian Yu

Yingchao Zhou

Yulong Wei

Kwanggyun Jang

Uzma B Rana

Techniques for business data protection for running tasks in a computer system are described herein. An aspect includes receiving a request. Another aspect includes processing a task corresponding to the request. Another aspect includes receiving a debugging request from a user corresponding to the task, wherein the debugging request is received during the processing of the task. Another aspect includes, based on receiving the debugging request, determining whether the user is authorized to access business data corresponding to the task. Another aspect includes, based on determining that the user is not authorized to access the business data corresponding to the task, redacting the business data from debugging data corresponding to the debugging request. Another aspect includes providing the redacted debugging data to the user.

Business data protection for running tasks in computer system

A data storage method includes: obtaining memory banks of arithmetic data; generating undetermined memory bank numbers of the memory banks sequentially; scanning storage dimensions of the arithmetic data to obtain the undetermined memory bank numbers, filling elements to make the undetermined memory bank numbers continuous if the undetermined memory bank numbers of two adjacent dimensions are not continuous; taking as a current transformation vector through a greedy algorithm a determined transformation vector where conflict is least and the number of the filling elements is smallest; generating current memory bank numbers of the memory banks according to the current transformation vector; converting each of the current memory bank numbers into a physical storage bank address through an offset function to obtain a corresponding internal offset address; and storing the arithmetic data into the memory banks according to the current memory bank numbers and the internal offset addresses.

Data storage and reading method and device

The present disclosure relates to a high-precision and high-efficiency laser polishing method oriented to a large-size ultra-thin mask plate, and belongs to the technical field of advanced laser manufacturing. A high-precision and high-efficiency laser polishing technology is applied to the surface smoothness improvement of the large-size ultra-thin mask plate. The high-precision and high-efficiency laser polishing method specifically comprises the four following steps: step one, selecting and placing an ultra-thin invar alloy mask plate on a five-axis machining platform; step two, adopting a nanosecond continuous laser, and setting a laser incident angle; step three, setting N laser polishing areas; and step four, performing laser polishing continuous splicing. Compared with the prior art, the surface smoothness of the mask plate is improved, the polishing efficiency is high, the precision is high, and the influence on the geometrical characteristic size of the appearance of an original mask plate is low.

High-precision and high-efficiency laser polishing method oriented to large-size ultra-thin mask plate

An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes sub-pixel units, and each sub-pixel unit includes a light emitting region and a non-light emitting region; each sub-pixel unit includes a light emitting element, the light emitting element includes a light emitting layer and a first electrode, and at least a part of the first electrode is in the light emitting region. A plurality of first wires are configured to supply a power signal to the light emitting element and include a first sub-wire; the first sub-wire includes a plurality of portions, adjacent two of the plurality of portions are spaced apart from each other by an opening in the light emitting region; at least a part of an orthographic projection of the opening on the array substrate does not overlap with an orthographic projection of the first electrode on the array substrate.

Array substrate with sub-pixels including power-supplying wire portions having openings therebetween and manufacturing method thereof, and display panel

A backplane, a display device and a method of manufacturing a backplane are provided. The backplane includes a base substrate; an inorganic layer on the base substrate, the inorganic layer including a plurality of protrusions; a metal layer covering atop of each protrusion and partial side wall near the top, the metal layer covering adjacent protrusions being disconnected; and a light-emitting layer covering the metal layer and the inorganic layer between the adjacent protrusions, the light-emitting layer being disconnected at regions of the protrusions not covered by the metal layer.

Display backplane with metal layer on protrusions

The present disclosure relates to a display device, a display panel, and a manufacturing method thereof. The display panel includes a substrate, a driving layer, and a display layer. The substrate has an opening area, a transition area surrounding the opening area, and a display area surrounding the transition area. The driving layer is disposed on a side of the substrate and covers at least the transition area and the display area, an area of the driving layer being located in the transition area being provided with a separation groove surrounding the opening area, the separation groove including a first groove body and a second groove body sequentially communicated toward the substrate in a direction perpendicular to the substrate, and a distance between bottom ends of side walls of the first groove body being smaller than a distance between top ends of side walls of the second groove body.

Display device and display panel

A display panel includes a display area and a first peripheral area located around the display area. A first gate driver is provided in the first peripheral area. The display panel is further provided with a plurality of first driving signal lines and a plurality of second driving signal lines. The plurality of first driving signal lines are arranged in a different layer from a layer in which the plurality of second driving signal lines are located. The m-th first driving signal line of the plurality of first driving signal lines and the k-th second driving signal line of the plurality of second driving signal lines are both electrically connected, in the first peripheral area, to an m-th output terminal of the first gate driver, where m is an integer greater than or equal to 1 and k is also an integer greater than or equal to 1.

Display panel and electronic apparatus

A display substrate and a preparation method thereof, and a display device are provided. The preparation method includes: forming a display region and a non-display region including an opening region; forming a first barrier wall between the display region and the opening region, in which the first barrier wall surrounds the opening region and includes a first metal layer structure, and a recess is formed on at least one side surface, surrounding the opening region, of the first metal layer structure; and after the first barrier wall is formed, forming a conductive layer pattern in the display region and on the first barrier wall. The forming the conductive layer pattern includes: forming a conductive material layer in the display region and on the first barrier wall, the conductive material layer being disconnected at the first barrier wall; and patterning the conductive material layer to form the conductive layer pattern.

Display substrate comprising metal layer structure in non-display region and with recessed side surface,preparation method thereof, and display device

The present disclosure includes artificial intelligence systems and methods for identifying grids for a geofence in an area in a map that includes a plurality of independently indexed regions of grids. The map is gridded into a plurality of grids and divided into a plurality of partitions. The methods include obtaining information of the geofence in the map, and determining a boundary grid series of the geofence from the plurality of grids. The methods include identifying at least one enclosed area in the geographical region, and upon determining that an enclosed area crosses two or more partitions, segmenting the enclosed area into two or more sub-areas. The methods also include determining boundary grids for each sub-area, and identifying internal grids in the sub-area for each sub-area. The methods further include identifying grids in the geographical region by collecting the boundary grids and the internal grids.

Systems and methods for identifying grids of geographical region in map

A display substrate has a display area and a peripheral area. The display substrate includes a base, a first insulating layer disposed above the base, a first alignment pattern disposed in the peripheral area on a surface of the first insulating layer facing away from the base, and a second alignment pattern disposed in the peripheral area at a side of the first insulating layer away from the base. An orthographic projection of the second alignment pattern on the base and an orthographic projection of the first alignment pattern on the base have a non-overlapping region therebetween, and the second alignment pattern is in contact with the first insulating layer in the non-overlapping region. Adhesion between the second alignment pattern and the first insulating layer is greater than adhesion between the second alignment pattern and the first alignment pattern.

Display substrate and method of manufacturing the same, and display panel

A display substrate having a fingerprint recognition region includes an array substrate, and a light shielding layer disposed at a side of the array substrate and at least located in the fingerprint recognition region. The material of the light shielding layer is an insulating material. A portion of the light shielding layer located in the fingerprint recognition region is provided with a plurality of light transmission holes, and each of the plurality of light transmission holes is configured to provide a transmission channel for fingerprint imaging light.

Display substrate and method for manufacturing the same, display apparatus

An array substrate comprises a display area and a periphery area; a common electrode is arranged at the display area, and an electrode bus is arranged at a periphery area and is close to the display area. The array substrate further comprises a first electrode pad, a first conductive portion, a second electrode pad, and a second conductive portion. The first electrode pad is arranged at the side, far away from the display area of the periphery area; the first conductive portion is connected with the first electrode pad and the common electrode; the second electrode pad is arranged at the side, far away from the display area of the periphery area; and the second conductive portion is connected to the second electrode pad, and extends to connect with the electrode bus along the direction far away from the first conductive portion.

Array substrate and display device

The disclosure provides a display substrate motherboard, a manufacturing method thereof, a display panel motherboard and a manufacturing method of a display substrate. The display substrate motherboard includes a base substrate including multiple substrate areas, each substrate area including a display region and a pad region; a display structure layer located on the base substrate and including a pixel defining layer and multiple film layers located between the pixel defining layer and the base substrate, a blocking region is arranged between any two adjacent substrate areas; a portion of the display structure layer in the blocking region has a first groove therein, a portion of the display structure layer between the first groove and the pad region adjacent thereto constitutes a first spacer region; a thickness of the portion of the display structure layer in the first spacer region is less than that in the display region.

Display substrate motherboard with blocking region and manufacturing method thereof, display panel motherboard and manufacturing method of display substrate

A processor initiates a run of a target container in a distributed computing environment. A processor detects at least one error occurring during the initiation of the target container. A processor determines at least one fix image based on the at least one error. A processor performs an error recovery of the target container based on the at least one fix image. A processor runs, in response to successfully performing the error recovery of the target container, the target container in the distributed computing environment.

Container recovery

Growing community of inventors

Ossining, NY, United States of America

Zhen Zhang