Montage Technology (shanghai) Co., Ltd.

Montage Lz Semiconductor (shanghai) Co., Ltd.

Montage Lz Technologies (chengdu) Co., Ltd.

Zhen Lu

Yuanfei Nie

Yu Chen

Gang Hu

Xiaomin Si

Xuepeng Wang

Ruifeng Lu

Qinghai Ren

The present application disclosed a decision feedback equalization processing device and method. The device comprises: a channel estimator for receiving an input signal, and determining, based on the input signal, an input signal autocorrelation matrix R, an input-output signal cross-correlation matrix Rand an input-output signal cross-correlation vector r; a tap coefficient calculator for receiving R, Rand r, and calculating a feed-forward equalizer (FFE) tap coefficient vector g and a feedback equalizer (FBE) tap coefficient vector f, wherein at least one of the FFE tap coefficient vector g and the FBE tap coefficient vector f is calculated using a conjugate gradient descent algorithm. The tap coefficient calculator comprises: a circulant matrix construction unit and a fast Fourier transformation (FFT) calculating unit. And the device further comprises a decision feedback equalizer for receiving from the tap coefficient calculator the FFE tap coefficient vector g and the FBE tap coefficient vector f, and performing equalization on the input signal and generating an equalized output signal.

Decision feedback equalization processing device and method

A digital signal receiver comprises an iterative decoder configured to decode its input signal using an iterative decoding algorithm, a signal quality detector, configured to detect signal quality of the input signal of the iterative decoder; a power consumption monitor, configured to detect a parameter indicating power consumption of the iterative decoder; a voltage regulator, configured to adjust a supply voltage of the iterative decoder to maintain it within a preset supply voltage range, based on the detected parameter indicating the power consumption of the iterative decoder; and an iteration controller, configured to adjust a maximum iteration number of decoding based on the signal quality of the input signal of the iterative decoder.

Digital signal receiver and method for controlling signal processing in such digital signal receiver

An interference processing method comprises: receiving a multi-carrier modulated signal, wherein the multi-carrier modulated signal comprises multi-carrier modulation symbols; discomposing the multi-carrier modulation symbols into a set of subcarriers, wherein the set of subcarriers at least comprises a target subcarrier; equalizing the target subcarrier to obtain an equalized target subcarrier; obtaining an error power of the equalized target subcarrier; and comparing the error power of the equalized target subcarrier with a predefined threshold to determine the existence of interference in the target subcarrier, wherein the predefined threshold is associated with a minimum distance between two constellation points of a modulation constellation of the target subcarrier.

Interference processing method and apparatus

A noise power estimator, comprising: a first subtractor configured to generate at least one first signal by subtracting a reconstructed interference signal from a symbol of a received first time-domain training sequence; a second subtractor configured to generate at least one second signal by subtracting an estimated value for the first time-domain training sequence from one of the at least one first signal; an averaging circuit configured to generate at least one square average value by average the at least part of the at least one second signals; and a detector configured to detect a minimum value among the at least one square average value and output the minimum value as a noise power estimation value.

Noise power estimator, receiver and method for noise power estimation

A channel estimator, comprises: a receiver receives a first time-domain training sequence; a first convolution circuit generates an estimated value for the first time-domain training sequence by convoluting a second time-domain training sequence with a current channel estimation value; a first subtractor generates an error by subtracting the estimated value for the first time-domain training sequence from the value of the first time-domain training sequence; an updating circuit generates an updated channel estimation value by updating the current channel estimation value with the error; the receiver iteratively receives a next symbol of the first time-domain training sequence, the first convolution circuit, the subtractor and the updating circuit repeat their operation until completion of receipt of a last symbol of the first time-domain training sequence. The updating circuit outputs the current updated channel estimation value upon completion of receipt of a last first time-domain training sequence.

Growing community of inventors

Shanghai, China

Zhen Lu