Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Zhen-Cheng Wu

Yung-Cheng Lu

Syun-Ming Jang Jang

Ying-Tsung Chen

Yen-Cheng Hu

Dian-Hau Chen

Cheng-Lin Huang

Yuh-Jier Mii

Shu-Hui Su

Pi-Tsung Chen

Chung-Chi Ko

Weng Chang

Jen-Chieh Chen

Po-Hsien Cheng

Jiing-Feng Yang

Ren-Guei Wu

Chi On Chui

Po-Hsiang Huang

You-Hua Chou

Yung-Chih Wang

Shwang-Ming Jeng

Nai-Wei Liu

Che-Lun Chang

Shuo-Wei Liang

Yi-Chen Ho

Peng Chen

Shwang-Ming Cheng

Yung-Chen Lu

Hsin-Feng Li

Yen-Hao Liao

Chen-Hua Douglas Yu

Tze-Liang Lee

Tien-I Bao

Mong-Song Liang

Yu-Lien Huang

Keng-Chu Lin

Da-Wen Lin

Lain-Jong Li

Chi-On Chui

Che-Hao Chang

Cheng-Hung Chang

Su-Horng Lin

Chia-Cheng Chou

Fang Wen Tsai

Chih-Lung Lin

Mong Song Liang

Hung Chun Tsai

Chih-Hung Sun

Chien-Jen Chen

Chun-Ming Lung

Tzu-Jen Chou

Tsung-Pao Chen

Jun-Wei Chen

I-i Chen

Cheng-Chang Kuo

Yun-Cheng Lu

Bi-Troug Chen

A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

Nanostructure field-effect transistor device and method of forming

In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.

Method of manufacturing semiconductor devices including forming an air gap based on removing a recessed sacrificial layer

A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.

Semiconductor device and method for forming the same

A method for forming a semiconductor device includes providing a base device having a top dielectric layer, forming a sacrificial layer on the top dielectric layer, and patterning the sacrificial layer to form openings. The method also includes depositing first protective dielectric layer and a low-K dielectric layer in the opening and performing planarization to form a first planarized structure including sacrificial regions and low k regions separated by a first protective layer. Next, top portions of the low-k dielectric layer are replaced with a second protective dielectric layer to form a second planarized structure that includes enclosed dielectric structures separated by sacrificial regions. The method further includes replacing the remaining portions of the sacrificial layer with a target metal interconnect material to form a third planarized structure that includes metal interconnect material disposed between enclosed dielectric structures.

Semiconductor device and method for manufacturing the same

A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.

Dielectric layer, interconnection structure using the same, and manufacturing method thereof

A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.

A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance.

Semiconductor structure having an air-gap region and a method of manufacturing the same

A method for fabricating back-contact type solar cells is provided. The method comprises forming a plurality of n-type doped zones, a plurality of p-type doped zones, and a back anti-reflection layer on a back surface of a semiconductor substrate. The lead-containing conductive paste may pass through the back anti-reflection layer and connect to the n-type doped zones and the p-type doped zones thereby being regarded as n-type electrodes and p-type electrodes.

Method for fabricating back-contact type solar cell

An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.

Impurity doped UV protection layer

A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.

A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.

Method of making a semiconductor device including barrier layers for copper interconnect

A solar cell includes a semiconductor substrate, a doping layer, a quantum well layer, a first passivation layer, a second passivation layer, a first electrode and a second electrode. The semiconductor substrate has a front surface and a back surface, and the front surface of the semiconductor substrate includes nano-rods. The doping layer covers the surface of the nano-rods. The electrode layers cover the doping layer. The quantum well layer having at least one first doping region and at least one second doping region is disposed on the semiconductor substrate. The quantum well layer includes polycrystalline silicon germanium (SiGe). The first passivation layer and the second passivation layer cover the first and the second doping regions of the quantum well layer, respectively. The first electrode and the second electrode are electrically connected to the first doping region and the second doping region of the quantum well layer, respectively.

Solar cell

A solar cell includes a semiconductor base, a first doped semiconductor layer, an insulating layer, a second doped semiconductor layer and a first electrode layer. The semiconductor base has a first doped type. The first doped semiconductor layer, disposed on the semiconductor base, has a doped contact region. The insulating layer is disposed on the first doped semiconductor layer, exposing the doped contact region. The second doped semiconductor layer is disposed on the insulating layer and the doped contact region. The first doped semiconductor layer, the doped contact region and the second doped semiconductor layer have a second doped type, and a dopant concentration of the second doped semiconductor layer is between that of the first doped semiconductor layer and that of the doped contact region. The first electrode layer is disposed corresponding to the doped contact region.

Solar cell and method of fabricating the same

A solar cell includes a semi-conductive substrate, a doping layer, an anti-reflection layer, an electrode, a passivation stacked layer and a contact layer. The semi-conductive substrate has a front and a back surface. The doping layer is disposed on the front surface. The anti-reflection layer is disposed on the doping layer. The electrode is disposed on the anti-reflection layer and electrically connected to the doping layer. The passivation stacked layer is disposed on the back surface and has a first dielectric layer, a second dielectric layer and a middle dielectric layer sandwiched between the first and the second dielectric layer. The dielectric constant of the middle dielectric layer is substantially lower than the dielectric constant of the first dielectric layer and the dielectric constant of the second dielectric layer. The contact layer covers the passivation stacked layer and electrically contacts with the back surface of the semi-conductive substrate.

A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.

Barrier layers for copper interconnect

Growing community of inventors

Hsinchu, Taiwan

Zhen-Cheng Wu