Samsung Electronics Co., Ltd.

Zhe Wu

Jinwoo Lee

Ja Bin Lee

Hideki Horii

Dong-Ho Ahn

Dongho Ahn

Jeong-Hee Park

Soon-Oh Park

Chungman Kim

Jin-Woo Lee

Kwangmin Park

Seunggeun Yu

Jabin Lee

Jin Woo Lee

Jeonghee Park

Seol Young Choi

Seung-Geun Yu

Wonjun Lee

Jae Ho Jung

Kiyeon Yang

Sung-Lae Cho

Changyup Park

Jung-hwan Park

Heeju Shin

Dong-Jun Seong

Dongsung Choi

Bonwon Koo

Hee Ju Shin

Chang Seung Lee

Segab Kwon

Jong Uk Kim

Dong Ho Ahn

Kyubong Jung

Gwangguk An

Kwang Min Park

Jeong Hee Park

Dong-jun Seong

Kyu-bong Jung

Kyu Bong Jung

Soyeon Choi

Dong Sung Choi

Ja-bin Lee

Jun-Ku Ahn

An operating method of a self-selecting memory device, includes an operation of applying a first write pulse corresponding to a first state to a first memory cell during a first pulse width, and an operation of applying a second write pulse corresponding to a second state to a second memory cell during a second pulse width, wherein the first write pulse and the second write pulse have substantially opposite polarities, wherein the first pulse width is longer than the second pulse width.

Self-selecting memory device, memory system having the same, and operating method thereof

A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.

Resistive memory device

A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.

Semiconductor memory device with selection patterns, storage patterns, and a gap fill layer and method for fabricating the same

A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

Resistive memory devices

A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.

Variable resistance memory device

A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

Semiconductor device

A memory device including a first conductive line on a substrate and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and a memory cell between the first conductive line and the second conductive line, the memory cell including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern, extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and having a tapered shape with a decreasing horizontal width along the vertical direction, wherein at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level.

Memory devices

A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern.

Switching element, variable resistance memory device, and method of manufacturing the switching element

A memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, and a plurality of memory cells each arranged between the first and second conductive lines and each including a variable resistance memory layer and a switch material pattern. The switch material pattern includes an element injection area arranged in an outer area of the switch material pattern, and an internal area covered by the element injection area. The internal area contains a first content of at least one element from arsenic (As), sulfur (S), selenium (Se), and tellurium (Te), the element injection area contains a second content of the at least one element from As, S, Se, and Te, and the second content has a profile in which a content of the at least one element decreases away from the at least one surface of the switch material pattern.

A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge&#x2014;Se&#x2014;Te, Ge&#x2014;Se&#x2014;Te&#x2014;As, and Ge&#x2014;Se&#x2014;Te&#x2014;As&#x2014;Si, and a composition ratio of arsenic (As) component of each of the Ge&#x2014;Se&#x2014;Te&#x2014;As and the Ge&#x2014;Se&#x2014;Te&#x2014;As&#x2014;Si being greater than 0.01 and less than 0.17.

Memory device, memory cell and method for programming memory cell

A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.

A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.

Memory device

A memory device is provided. The memory device includes a variable resistance layer. A selection device layer is electrically connected to the variable resistance layer. The selection device layer includes a chalcogenide switching material having a composition according to chemical formula 1 below,[GeSeTe][X]&#x2003;&#x2003;(1)

Memory device including a variable resistance material layer

A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.

Variable resistance memory devices

A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below,[GeSi(AsTe)][N]&#x2003;&#x2003;(1)

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Suwon-si, South Korea

Zhe Wu