Intel Corporation

Advanced Micro Devices Corporation

Oracle International Corporation

Zhe Wang

Alaa R Alameldeen

Zeshan A Chishti

Christopher B Wilkerson

Yi Xu

Junli Gu

Christopher J Hughes

Arun Theebaprakasam

Ting Cao

Shih-Lien L Lu

Bradford Michael Beckmann

Sooraj Puthoor

Muthukumar Swaminathan

Buddhika Kottahachchi

Kuang-Yu Shih

Seth H Pugsley

Yuan Xie

Lingxiang Xiang

Kwan-I Lee

Travis T Schluessler

Andrew V Anderson

Rajat Agarwal

Wei Wu

Lidia Warnes

Nagi Aboulenein

Gary Smith

Yi Zou

Andrew M Rudoff

Himanshu Sharma

Ramaprakash Hosalli Sathyanarayan

Binh Q Pham

Keqiang Wu

Fannie Ho

Andy M Rudoff

Kunal A Khochare

Jason A Gayman

Shuchang Shan

Charles Moidel

Rafal Rudnicki

Xie Yuan

Shuai Mu

Gordon King

Thomas Petersen

Heidi Pan

Elvira Teran

In one embodiment, a processor includes interconnect circuitry, processing circuitry, a first cache, and cache controller circuitry. The interconnect circuitry communicates over a processor interconnect with a second processor that includes a second cache. The processing circuitry generates a memory read request for a corresponding memory address of a memory. Based on the memory read request, the cache controller circuitry detects a cache miss in the first cache, which indicates that the first cache does not contain a valid copy of data for the corresponding memory address. Based on the cache miss, the cache controller circuitry requests the data from the second cache or the memory based on a current bandwidth utilization of the processor interconnect.

Dynamic cache coherence protocol based on runtime interconnect utilization

Methods, devices, and systems for managing performance of a processor having multiple compute units. An effective number of the multiple compute units may be determined to designate as having priority. On a condition that the effective number is nonzero, the effective number of the multiple compute units may each be designated as a priority compute unit. Priority compute units may have access to a shared cache whereas non-priority compute units may not. Workgroups may be preferentially dispatched to priority compute units. Memory access requests from priority compute units may be served ahead of requests from non-priority compute units.

System performance management using prioritized compute units

An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.

Inter-cluster shared data management in sub-NUMA cluster

A processor that includes compression instructions to compress multiple adjacent data blocks of uncompressed read-only data stored in memory into one compressed read-only data block and store the compressed read-only data block in multiple adjacent blocks in the memory is provided. During execution of an application to operate on the read-only data, one of the multiple adjacent blocks storing the compressed read-only block is read from memory, stored in a prefetch buffer and decompressed in the memory controller. In response to a subsequent request during execution of the application for an adjacent data block in the compressed read-only data block, the uncompressed adjacent block is read directly from the prefetch buffer.

Processor instructions for data compression and decompression

Methods, systems and apparatuses may provide for technology that determines measured timing data in response to a presentation request from an application, wherein the measured timing data is associated with one or more previous frames and the presentation request is associated with one or more subsequent frames. The technology may also determine scheduling times for the subsequent frame(s) based on the measured timing data, wherein the scheduling times include a simulation time, a rendering time, a driver submission time, a hardware submission time, and a display time. In one example, the technology controls a pacing of the subsequent frame(s) on a display in accordance with the scheduling times.

Frame pacing for improved experiences in 3D applications

Examples herein relate to checkpoint replication and copying of updated checkpoint data. For example, a memory controller coupled to a memory can receive a write request with an associated address to write or update checkpoint data and track updates to checkpoint data based on at least two levels of memory region sizes. A first level is associated with a larger memory region size than a memory region size associated with the second level. In some examples, the first level is a cache-line memory region size and the second level is a page memory region size. Updates to the checkpoint data can be tracked at the second level unless an update was previously tracked at the first level. Reduced amounts of updated checkpoint data can be transmitted during a checkpoint replication by using multiple region size trackers.

Virtual machine replication and migration

An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinning

A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory

An apparatus is described. The apparatus includes memory controller logic circuitry to interface to a multi-level memory having a higher memory level to act as a memory side cache for a lower memory level. The memory controller logic circuitry having policy determination circuitry to prevent lesser accessed data items from occupying space in the higher memory level at the expense of more frequently accessed data items.

Caching bypass mechanism for a multi-level memory

One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.

Cache architecture using way ID to reduce near memory traffic in a two-level memory system

An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

Method and apparatus for multi-level memory early page demotion

An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.

Coarse tag replacement

In one embodiment, aggregated write back in a direct mapped two level memory in accordance with the present description, aggregates a dirty block or other subunit of data being evicted from a near memory of a two level memory system, with other spatially co-located dirty subunits of data in a sector or other unit of data for write back to a far memory of the two level memory system. In one embodiment, dirty spatially co-located subunits are scrubbed and aggregated with one or more spatially co-located dirty subunits being evicted. In one embodiment, a write combining buffer is utilized to aggregate spatially co-located dirty subunits prior to being transferred to a far memory write buffer in a write back operation. Other aspects are described herein.

Aggregated write back in a direct mapped two level memory

A privileged account management system is provided that controls the management and access of resources within the organization. Resources may include target systems and accounts of the organization. In an embodiment, the privileged account management system is configured to enable the creation of one or more resource groups. A resource group includes a subset of a plurality of resources provided by the organization. In certain embodiments, the privileged account management system is configured to define one or more groups of administrative entities within the organization and assign to each administrative entity in a group of administrative entities, a set of privileges on a resource group. In certain embodiments, the privileged account manager system may be configured to enable an administrative entity from a group of administrative entities to delegate a subset of privileges associated with a resource group to a user entity not in the group of administrative entities.

Delegated privileged access grants

Growing community of inventors

Hillsboro, OR, United States of America

Zhe Wang