Omnivision Technologies, Inc.

Zhe Gao

Tiejun Dai

Ling Fu

Yu-Shen Yang

Zhiyong Zhan

Qing Qin

Rui Wang

Hiroaki Ebihara

Keiji Mabuchi

Liang Zuo

Shoushun Chen

Dennis Tunglin Lee

Min Qu

Yingkan Lin

Chengcheng Xu

Chun-Hsiang Chang

Xuelian Liu

Tomas Geurts

Jingwei Lai

Pixel designs with reduced LOFIC reset and settling times are disclosed herein. In one embodiment, a pixel cell includes a photosensor configured to photogenerate image charge in response to incident light, a floating diffusion to receive the image charge from the photosensor, a transfer transistor coupled between the floating diffusion and the photosensor to transfer the image charge to the floating diffusion, and a first reset transistor coupled between the floating diffusion and the voltage supply. The pixel cell further includes a capacitor having two ends, and a second reset transistor. A first end of the capacitor is coupled to the floating diffusion. The second reset transistor is coupled between a second end of the capacitor and the voltage supply.

Pixel designs with reduced LOFIC reset and settling times

A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.

CAPMID design in VRFD for HDR structure

An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

Real GS and OFG timing design for 1-by-2 shared HDR VDGS

A global shutter readout circuit includes a pixel enable signal and a first sample and hold (SH) signal that are configured to turn ON a pixel enable transistor and a first storage transistor at a first time during a global transfer period. The pixel enable signal is configured to begin a transition to an OFF level at a second time and complete the transition to the OFF level at a third time to turn OFF the pixel enable transistor. The first SH signal is configured to begin a transition to the OFF level at a fourth time, which occurs after the second and third times, and complete the transition to the OFF level at a fifth time to turn OFF the first storage transistor. An OFF transition duration between the fourth and fifth times is greater than an ON transition duration of the first SH signal at the first time.

Voltage domain global shutter readout circuit timing

A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bitline. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

Voltage domain global shutter readout circuit

A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

Sample and hold switch driver circuitry with slope control

An event driven pixel includes a photodiode configured to photogenerate charge in response to incident light received from an external scene. A photocurrent to voltage converter is coupled to the photodiode to convert photocurrent generated by the photodiode to a voltage. A filter amplifier is coupled to the photocurrent to voltage converter to generate a filtered and amplified signal in response to the voltage received from the photocurrent to voltage converter. A threshold comparison stage is coupled to the filter amplifier to compare the filtered and amplified signal received from the filter amplifier with thresholds to asynchronously detect events in the external scene in response to the incident light. A digital time stamp generator is coupled to asynchronously generate a digital time stamp in response to the events asynchronously detected in the external scene by the threshold comparison stage.

Digital time stamping design for event driven pixel

An event driven sensor includes an arrangement of photodiodes including an inner portion laterally surrounded by an outer portion. An outer pixel cell circuit is coupled to generate an outer pixel value in response to photocurrent generated by the outer portion. The outer pixel value is a binned signal representative of an average value of brightness of incident light on the arrangement of photodiodes. An inner pixel cell circuit is coupled to the inner portion to generate an inner pixel value in response to photocurrent generated by from the inner portion. An event driven circuit is coupled to the outer pixel cell circuit and the inner pixel cell circuit. The event driven circuit is coupled to generate an output signal responsive to an inner brightness indicated by the inner pixel value relative to an outer brightness indicated by the outer pixel value.

Event driven pixel for spatial information extraction

Switching techniques for fast voltage settling in image sensors are described. In one embodiment, an image sensor includes a plurality of lateral overflow integrating capacitor (LOFIC) pixels arranged in rows and columns of a pixel array. The plurality of pixels includes an active pixel configured for exposure to light, and a dummy pixel at least partially protected from exposure to light. A common bitline (BL) is couplable to the active pixel and the dummy pixel. A comparator (OA) is coupled to the bitline. The comparator is configured to receive a pixel voltage (Vx) from the active pixel on one input and a ramp voltage (Vy) on another input. Charge accumulated by the active pixel is determined at least in part by an intersection between the ramp voltage and the pixel voltage.

Auto-zero techniques for lateral overflow integrating capacitor (LOFIC) readout image sensor

Switching techniques for fast voltage settling in image sensors are described. In one embodiment, a transfer gate (TX) driver circuit of an image sensor includes a TX driver configured to provide a TX driver voltage to a plurality of pixels of an image sensor. A power supply (NVDD) is operationally coupled to the TX driver. A first switch (SW) operationally coupling an outside capacitance (Cext) and the TX driver. A second switch (SW) operationally coupling the Cext and the NVDD. A third switch (SW) operationally coupling the NVDD and the TX driver. A falling edge of the TX driver voltage is configured to control a start of data transfer from individual pixels of the plurality of pixels. The SWand the SWare configured in an open position before the falling edge of the TX driver voltage. The SWis configured in a closed position before the falling edge.

Switching techniques for fast voltage settling in image sensors

An image sensor includes a source follower coupled to a photodiode to generate an image signal responsive to photogenerated charge. The image signal is received by image readout circuitry through a row select transistor. A reset transistor resets the photogenerated charge. A first node of mode select circuit is coupled to the reset transistor, a second node is coupled to a pixel supply voltage, and a third node is coupled to an event driven circuit. The mode select circuit couples the first node to the second node during an imaging mode to supply the pixel supply voltage to the reset transistor. The mode select circuit is further configured to couple the first node to the third node during an event driven mode to couple a photocurrent of the photodiode to drive the event driven circuit through the reset transistor to detect changes in the photocurrent.

Hybrid CMOS image sensor with event driven sensing

A pixel cell includes a first subpixel and a plurality of second subpixels. Each subpixel includes a photodiode to photogenerate image charge in response to incident light. Image charge is transferred from the first subpixel to a floating diffusion through a first transfer transistor. Image charge is transferred from the plurality of second subpixels to the floating diffusion through a plurality of second transfer transistors. An attenuation layer is disposed over the first subpixel. The first subpixel receives the incident light through the attenuation layer. The plurality of second subpixels receive the incident light without passing through the attenuation layer. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A capacitor is coupled to the DFD transistor.

High dynamic range CMOS image sensor design

A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched.

An image sensor includes a pixel array with active rows of pixel cells, a black level calibration row with black image data generation circuits coupled to generate black image data signals representative of an absence of the incident light, and a dummy row with black level clamping circuits coupled to receive a black sun reference voltage to clamp bitlines of the pixel array, and a black level calibration circuit coupled to receive the black sun reference voltage to generate a black sun calibration voltage. A black sun feedback circuit is coupled to generate the black sun reference voltage in response to the black sun calibration voltage and a black level sample reference, and a black level sampling circuit is coupled to the bitlines to sample the black image data signals to generate the black level sample reference received by the black sun feedback circuit.

Image sensor with frame level black level calibration

A readout circuit for use in an image sensor includes a first sample and hold (SH) circuit coupled to a bitline that is coupled to a pixel array. A second SH circuit is coupled to the bitline. A bypass switch is coupled to the bitline, the first SH circuit, and the second SH circuit. An analog to digital converter (ADC) is coupled to the bypass switch. The bypass switch is configured to provide an image charge value from the pixel array to the ADC through the bitline, or through one of the first SH circuit or the second SH circuit in response to a switch select signal.

Growing community of inventors

San Jose, CA, United States of America

Zhe Gao