Yangtze Memory Technologies Co., Ltd.

Zhaosong Li

Li Hong Xiao

Yu Ting Zhou

Zhao Hui Tang

Sizhe Li

Qian Tao

Zhenyu Lu

Yushi Hu

Jun Chen

Jin Wen Dong

Yue Qiang Pu

Jian Xu

Zongliang Huo

Jun Liu

Sha Sha Liu

Ji Xia

Haohao Yang

Xiaowang Dai

Jing Gao

Enbo Wang

Jing Liu

Jialan He

EnBo Wang

Feng Lu

Chuanhai Shan

Zhouyang Lu

Three-dimensional (3D) NAND memory devices and methods are provided. A fabrication method includes forming a semiconductor layer over a substrate, forming an opening that extends partially through the semiconductor layer, depositing a first stack layer and a second stack layer that are alternately stacked over a sidewall of the opening and over the semiconductor layer, and filling the opening with a dielectric material to form an alignment mark.

Three dimensional (3D) memory device and fabrication method

Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Multiple-stack three-dimensional memory device and fabrication method thereof

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Memory device and forming method thereof

Disclosed is a method for forming a staircase structure of 3D memory devices, comprising (i) forming a stack of layers on a substrate; (ii) removing a portion of the stack to form a lower region and a upper region; (iii) forming a mask to cover the lower region and the upper region of the stack; (iv) forming a first opening in the mask to expose a first portion of the stack in the lower region and a second opening in the mask to expose a second portion of the stack in the upper region; (v) forming a photoresist layer to cover the stack and the mask; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases in the first opening and the second opening; (vii) removing the photoresist layer and the mask; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Method for forming staircase structure of three-dimensional memory device

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces.

Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.

Wafer flatness control using backside compensation structure

Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.

Methods of semiconductor device fabrication

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Embodiments of a method for forming a staircase structure of 3D memory devices are disclosed. The method comprises (i) forming an alternating layer stack including multiple layers disposed on a substrate in a vertical direction; (ii) removing a portion of the alternating layer stack to form multiple step-platforms in a staircase region of the alternating layer stack; (iii) forming a hard mask layer to cover top surfaces of the step-platforms; (iv) forming multiple openings in the hard mask layer to expose a portion of each of the step-platforms; (v) forming a photoresist layer to cover the top surfaces of the step-platforms and the hard mask layer; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases on each of the step-platforms; (vii) removing the photoresist layer and the hard mask layer; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Growing community of inventors

Hubei, China

Zhaosong Li