Tsinghua University

Zhaoshi Li

Shaojun Wei

Leibo Liu

Shouyi Yin

Guiqiang Peng

Yansheng Wang

The present disclosure provides a method and an apparatus for processing concurrent transactions, and a non-transitory computer readable storage medium. The method includes: determining whether a two-dimensional digraph for a set of concurrent transactions has a cyclic structure, wherein the set of concurrent transactions comprises a transaction to be committed and at least one committed transaction, the two-dimensional digraph comprises a plurality of nodes corresponding respectively to the transactions in the set, and directed edges between the nodes of the two-dimensional digraph indicate a serializability relation among the transactions in the set; aborting the transaction to be committed if it is determined that the two-dimensional digraph has the cyclic structure; and committing the transaction to be committed if it is determined that the two-dimensional digraph does not have the cyclic structure. Embodiments of the present disclosure can improve the performance of a concurrent system.

Method and apparatus for processing concurrent transactions, and storage medium

A method and a device for processing an irregular application are disclosed. The method comprises: determining M classes of tasks of the irregular application; executing the M classes of tasks in parallel, wherein each task has an index respectively; for the i-th task in the x-th class of task of the M classes of tasks: when the i-th task is executed to a rendezvous, stalling the i-th task, and determining a rule corresponding to the i-th task; inspecting current state of the i-th task according to the rule corresponding to the i-th task so as to steer the continued execution of the i-th task. According to the embodiment of the present disclosure, irregular applications can be correctly and automatically executed with high performance in a manner of fine-grained pipeline parallelism.

Method and device for processing an irregular application

Provided is a method for generating configuration information of a dynamic reconfigurable processor. The dynamic reconfigurable processor includes a processing unit array, and the processing unit array includes a plurality of processing units. The method includes steps of: reading information of a task to be executed and generating an array configuration information top of the processing unit array according to the information; generating a plurality of processing unit configuration information corresponding to the plurality of processing units respectively according to the information; and assembling the array configuration information top and the plurality of processing unit configuration information.

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Jiangsu, China

Zhaoshi Li