International Business Machines Corporation

Zhaoqing Chen

Matteo Cocchini

Tingdong Zhou

Rohan U Mandrekar

Wiren Dale Becker

Hubert Harrer

George A Katopis

Christian Schuster

Stephen Bruce White

John William Zack

Thaddeus Chen

Jan Elizabeth Hoffman

Susan Marie Karwoski

Joonsuk Park

Jan Elizabeth Garrett-Hoffman

Edwin Scott Reichmann

A method of forming a mixed mode response from a single ended mode input includes modeling a first voltage controlled current source based on relative values of a vinput signal and a vinput signal and modeling a second voltage controlled current source based on relative values of the vinput signal and the vinput signal. A method of forming a single ended mode response from a mixed mode input modeling a first voltage controlled current source based on relative values of a vinput signal and a vinput signal and modeling a second voltage controlled current source based on relative values of the vinput signal and the vinput signal, the second voltage controlled being connected to ground through a second terminating impedance that is equal to the reference impedance (Z).

Single-ended-mode to mixed-mode transformer spice circuit model for high-speed system signal integrity simulations

Embodiments of the present invention are directed to a computer-implemented method of simulating forward traveling voltages in a simulated circuit. The method includes inserting a traveling wave probe, via a processor, at an observation point of a simulated transmission line. The processor applies a first signal at an input of the traveling wave probe, and evaluates an output of the traveling wave probe. The processor next determines an instantaneous wave forward voltage and an instantaneous wave backward voltage at the traveling wave probe, and displays the instantaneous wave forward voltage and the instantaneous wave backward voltage via an output device.

Transient and AC simulations with traveling wave probe circuit

A method of analyzing a transient response of an electronic circuit includes receiving at a jitter modulator circuit first and second input signals, modulating the second input signal on the first input signal in the jitter modulator circuit and outputting a modulated signal based on the first and second input signals. The jitter modulator circuit includes models of N parallel connected transmission lines and modulating includes providing the first input signal, at each of a series of times t, to the N transmission line models and selecting an output of two of the N transmission line models based on the second input. The modulated signal is formed based on the selected outputs of the two N transmission lines models.

Behavioural circuit jitter model

A method of analyzing a transient response of an electronic circuit is includes: forming a model of a retimer that includes a data clocked latch; providing a latch input signal at the input of the model; forming an output signal based on the latch input signal with the voltage controlled voltage source, wherein the voltage controlled voltage source provides a high output when the latch input signal passes through a low to high transition value and continues to provide the high output until the latch input signal passes through a high to low transition value.

Data clocked retimer model

Single ended-mode to mixed-mode transformer spice circuit model for high-speed system signal integrity simulations

An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

Interconnect array pattern with a 3:1 signal-to-ground ratio

A method to generate a reduced delay twinaxial SPICE model is provided. The method may include measuring near-end S-parameter components and far-end S-parameter components of a twinaxial cable, reducing an original time delay of the far-end S-parameter components by multiplying each of the far-end S-parameter components by a complex exponential based on an equivalent delay length, a signal frequency, and an effective dielectric constant, simulating a signal transmitted across a twinaxial cable by running a 4-port SPICE model using the near-end S-parameter components and the multiplied far-end S-parameter components, and recording a magnitude and a phase of the transmitted signal with respect to frequency as outputs of the reduced delay twinaxial SPICE model.

Spice circuit model for twinaxial cable

A method of analyzing a transient response of an electronic circuit includes forming a model of a retimer and receiving an analyzing the output signal of the retimer. The model includes: a signal input circuit that receives an input signal; a clock input circuit that receives a reference clock signal; a slicer that samples a signal produced by the signal input circuit based on the reference clock signal; and an output signal circuit that forms an output signal from a sample taken by the slicer and that is based on the reference clock signal.

Reference clocked retimer model

One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.

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Poughkeepsie, NY, United States of America

Zhaoqing Chen