Dongfang Jingyuan Electron Limited

Zhongke Jingyuan Electron Limited

Hermes Microvision Inc.

Zhaoli Zhang

Jie Lin

Weimin Ma

Zongchang Yu

Hua-yu Liu

Naihong Tang

Wei Fang

Jack Jau

Yan Zhao

Jian Zhang

Xiaomei Wu

Kangkang Yang

Methods and apparatuses are provided for data processing. The method includes receiving a first data packet and a second data packet; associating first codes with the first data packet and second codes with the second data packet to generate a combined data packet after receiving the first data packet and the second data packet, wherein the first codes and the second codes specify processing to be performed to the a combined data packet; generating the combined data packet comprising the first data packet and the second data packet in response to determining that the first data packet and the second data packet are correlated; and performing the processing to the combined data packet in accordance with the first codes or the second codes.

Method and apparatus for data processing

Methods and apparatuses are provided for data processing. The method includes receiving a data packet; associating codes with the data packet, wherein the codes specify processing to be performed to the data packet; and performing the processing to the data packet in accordance with the codes. The apparatus includes a receiver, configured to receive a data packet; a processor; and a memory coupled to the processor, the memory configured to store instructions which when executed by the processor become operational with the processor to: associate codes with the data packet, wherein the codes specify processing to be performed to the data packet; and perform the processing to the data packet in accordance with the codes.

Methods, apparatuses, and systems for image-based abnormality detection for periodic patterns are provided. The method includes receiving an image pattern T determined from an inspection image, wherein T comprises multiple periodic segments along a spatial direction; determining, by a processor, a first reference pattern R1 by rearranging the multiple periodic segments of T in a first manner and a second reference pattern R2 by rearranging the multiple periodic segments of T in a second manner; determining whether an abnormality exists in T by comparing a part of T with a part of R1 and a part of R2; and determining that the abnormality exists in T based on a determination that the part of T is different from the part of R1 and the part of R2.

Abnormality detection for periodic patterns

Methods and systems for identifying defects in an integrated circuit are provided. The method includes receiving input data of a pattern associated with an integrated circuit, determining feature data associated with features of the pattern using the input data, determining defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determining a defect identification result using the defect detection results. The system includes a processor and a memory. The memory is coupled to the processor and configured to store a set of instructions to receive input data of a pattern associated with an integrated circuit, determine feature data associated with features of the pattern using the input data, determine defect detection results associated with the pattern using the input data, the feature data, and defect detection techniques, and determine a defect identification result using the defect detection results.

Method and system for identifying defects of integrated circuits

Methods and systems for inspecting integrated circuits are provided. The method includes monitoring an inspection of integrated circuits to receive inspection data including machine data and defect detection results, storing the inspection data in a database, modifying, via the database, at least one of a plurality of recipe files associated with the inspection based on the machine data, and modifying, via the database, at least one of a plurality of software parameters associated with the inspection based on the defect detection results. The system includes a memory including instructions executable by a processor to monitor an inspection of integrated circuits to receive and store inspection data including machine data and defect detection results in a database, modify, via the database, a recipe file associated with the inspection based on the machine data, and modify, via the database, a software parameter associated with the inspection based on the defect detection results.

Dynamic updates for the inspection of integrated circuits

Methods and systems for inspecting integrated circuits are provided. The method includes generating care areas that each includes at least one potential defect, organizing the generated care areas based on a first set of spatial relationships to provide a list of neighboring care areas, wherein each neighboring care area is an entry within the list, and generating a recipe file of the list, wherein each neighboring care area is inspected sequentially using a high-resolution inspection system. The system comprises a memory including instructions executable by a processor to: generate care areas that each includes at least one potential defect, organize the generated care areas based on a first set of spatial relationships to provide a list of neighboring care areas that are each an entry within the list, and generate a recipe file of the list, wherein each neighboring care area is inspected sequentially using a high-resolution inspection system.

Care area generation for inspecting integrated circuits

Methods, apparatuses and systems for classifying defects for a defect inspection system are disclosed. The defect inspection system can be used to inspect and manage wafer or reticle defects. The method includes receiving a defect record based on an inspection of a target specimen, the defect record comprising a defect image associated with an unknown defect, selecting, by a computing device using a first processing unit, components ranked by significance from the defect image using a first learning technique, and determining, by the computing device using the first processing unit, whether the defect image is associated with a known defect type based on the components ranked by significance using a second learning technique.

Learning based defect classification

Methods and systems for defect prediction are provided. The method includes receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC, and determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system. Based on the provided methods and systems, care areas can be generated incorporating actual process conditions when the inspected IC is being manufactured, and fast and high-resolution IC defect inspection systems can be implemented.

Method and system for defect prediction of integrated circuits

A method and system for detecting defects of integrated circuits have been provided. The method comprises generating process sensitive patterns of an integrated circuit, scanning the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determining care areas of the integrated circuit using the process condition parameters, and scanning the care areas using the high-resolution system to detect at least one defect of the integrated circuit. The system comprises a processor and a memory with instructions executable by the processor to generate process sensitive patterns of an integrated circuit, scan the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determine care areas of the integrated circuit using the process condition parameters, and scan the care areas using the high-resolution system to detect at least one defect of the integrated circuit.

Guided defect detection of integrated circuits

A method for managing defects for an augmented automatic defect classification (ADC) process is disclosed. The method includes receiving a defect record based on an inspection of a target specimen; extracting, from a design database, relevant design data associated with a patch surrounding a location of a defect from the defect record; performing, by a processor, lithographic simulation on the relevant design data associated with the patch to determine a context patch; comparing, by the processor, the context patch with an image of the defect from the defect record to determine whether there exists a match between the context patch and the image of the defect; and defining the defect as a systematic defect based on a determination that there exists a match between the context patch and the image of the defect.

Augmented automatic defect classification

A method of classifying the defects on a wafer having some same chips and corresponding system is provided. After receiving images formed by scanning the wafer using a charged particle beam, these images are examined such that both defective images and defect-free images are found. Then, the defect-free images are translated into a simulated layout of the chip, or a database is used to provide the simulated layout of the chip. Finally, the defects on the defective images are classified by comparing the images with the simulated layout of the chip. The system has some modules separately corresponds to the steps of the method.

Growing community of inventors

San Jose, CA, United States of America

Zhaoli Zhang