Tianma Micro-electronics Co., Ltd.

Shanghai Tianma Micro-electronics Co., Ltd.

Shanghai Avic Opto Electronics Co., Ltd.

Xiamen Tianma Micro-electronics Co., Ltd.

Wuhan Tianma Micro-electronics Co., Ltd

Other

Shanghai Tianma Micro-electronics., Ltd.

Zhaokeng Cao

Yihua Zhu

Qingjun Lai

Dandan Qin

Tianqing Hu

Yong Yuan

Ping An

Wantong Shao

Poping Shen

Gang Liu

Zhongshou Huang

Yao Lin

Tingting Cui

Xiufeng Zhou

Yangzhao Ma

Yinghua Mo

Kerui Xi

Shoufu Jian

Long Zhang

Zhaodong Zhang

Guofeng Zhang

Bo Li

Tinghai Wang

Huijun Jin

Zhiqiang Xia

Ting Zhou

Huangyao Wu

Linshan Guo

Xiaoye Li

Shulin Yao

Chao Wang

Gaojun Huang

Boping Shen

Shui He

Shaorong Yu

Zhongjie Zhang

Di Zhu

Chunmei Gao

Wenze Shan

Xingyao Zhou

Xiao Li

Jun Wei Zhang

Jun Li

Yumin Xu

Kang Yang

Lei Zhang

Lei Huang

Zheng Wang

Chen Liu

Hongbo Zhou

Gujun Li

Kangpeng Yang

Junhui Lou

Juan Zhu

Xianxiang Zhang

Yongxin He

Chaohuang Pan

Min Cai

Yingying Xu

Qiong Song

Yanan Wang

Longcai Xin

Xiaodong Luo

Zhiwei Zhou

Yansong Li

Miaomiao Wang

Qian Yang

Yujie Zhao

Jiaxiang Dai

Huanda Wu

Yongjun Wu

Xiangmin Tan

Yan Jia

Zhou Ye

Ke Guo

Xuan Lu

Shihu Su

A display panel includes at least one driving circuit and at least one pixel circuit. A driving circuit of the at least one driving circuit provides a driving signal for a pixel circuit of the at least one pixel circuit. The driving circuit includes N-level shift registers cascaded with each other. N is greater than or equal to two. The pixel circuit provides a display signal for a display unit of the display panel. A shift register of the N-level shift registers includes at least one first transistor. The at least one first transistor includes at least one first active layer, and an active layer with a largest area among the at least one first active layer is a first preset active layer. The pixel circuit includes at least one second transistor. The at least one second transistor includes at least one second active layer.

Display panel and display device

A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.

A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D. A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L. A sixth area S=L×D

A display panel includes a base substrate, a first transistor, and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. A length of a channel region of the second transistor is L2. Along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2.

A display panel includes a pixel circuit and a driving circuit. The pixel circuit includes a driving transistor. The driving circuit is configured to provide a signal for the pixel circuit, receive a third voltage signal and a fourth voltage signal, and generate an output signal. The third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal. A working process of the pixel circuit includes a reset phase and a bias phase. The output signal of the driving circuit is a reset signal in the reset phase. The output signal of the driving circuit is a bias signal in the bias phase. In response to the driving transistor being a PMOS transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal.

A display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, N≥2. A shift register of the N levels of the shift registers includes a third control unit and a fourth control unit. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node. The first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The fourth control unit is configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the first node and the signal of the fourth node and includes a first transistor and a second transistor.

A display panel includes a shift register, a pixel circuit, and a driving circuit. The shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node.

A display panel and a display device are provided. The display panel includes at least one driving circuit and at least one pixel circuit. A driving circuit provides a driving signal for a pixel circuit. The driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register includes at least one first active layer, and an active layer with a largest area is a first preset active layer. The pixel circuit includes at least one second active layer, where an active layer with a largest area among active layers containing silicon is a second preset active layer, and an active layer with a largest area among active layers containing oxide semiconductor is a third preset active layer. The first preset active layer has an area greater than the second preset active layer and the third preset active layer.

A display panel and a display device are provided in the present disclosure. The display panel includes a base substrate, a first transistor, a second transistor, a pixel circuit, and a drive circuit. A first active layer of the first transistor includes silicon; and a second active layer of the second transistor includes an oxide semiconductor. A length of a channel region of the first transistor is LL a distance between a first gate electrode and the first active layer is D1, and a first area S1=L1&#xd7;D1; and a length of a channel region of the second transistor is L2, a distance between a second gate electrode and the second active layer is D2, and a second area S2=L2&#xd7;D2, where S1&#x3c;S2. The second transistor is included in the drive circuit, and the first transistor is included in one of the pixel circuit and the drive circuit.

A display panel and a display apparatus are provided. The display panel has a conventional display region and a function display region for arranging an optical function element, and includes first pixel circuits and first fixed potential lines that are located in the conventional display region and electrically connected to the first pixel circuits, and further includes second pixel circuits and second fixed potential lines that are located in the function display region and are electrically connected to the second pixel circuits. A distance between two adjacent first fixed potential lines of the first fixed potential lines is greater than a distance between two adjacent second fixed potential lines of the second fixed potential lines.

Display panel and display apparatus

A display panel and a display device are provided. A shift register of the display panel includes a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal; a third control unit, configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node; and a fourth control unit, configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signals of the second node and the fourth node.

An inverter, a method for driving an inverter, a driving circuit and a display panel are provided. An inverter includes a first module; a second module; an initial signal input terminal; and a first level signal input terminal. The first module includes a first transistor, a second transistor, and a third transistor; control terminals of the first transistor and the second transistor are both electrically connected to the initial signal input terminal; a first terminal of the third transistor is electrically connected to the first level signal input terminal; a first terminal of the second transistor is electrically connected to a first terminal of the second transistor; a second terminal of the second transistor is electrically connected to a control terminal of the third transistor; the first module includes a leakage current control component at least electrically connected with the second terminal of the first transistor.

Inverter and driving method thereof, driving circuit and display panel

A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, where N2. A shift register of the N levels of shift registers includes: a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, configured to receive a first voltage signal and a second voltage signal, and control a signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal; and a third control unit, configured to receive the first voltage signal and the second voltage signal, and control an output signal in response to the signal of the second node and a signal of the third node.

A display panel and a display apparatus are provided. The display panel has a conventional display region and a function display region for arranging an optical function element, and includes first pixel circuits and first fixed potential lines that are located in the conventional display region and electrically connected to the first pixel circuits, and further includes second pixel circuits and second fixed potential lines that are located in the function display region and are electrically connected to the second pixel circuits. mfirst pixel circuit groups are provided between two adjacent first fixed potential lines, msecond pixel circuit groups are provided between two adjacent second fixed potential lines, mand mare each a positive integer greater than or equal to 1, and m&#x3e;m

Display panel for reducing number of fixed potential lines in function display region, and display apparatus

Disclosed are an electro-static discharge circuit, an array substrate, a display panel and a display apparatus. The electro-static discharge circuit includes a first transistor, a second transistor, a first switching device and a second switching device. A first end of the first transistor is electrically connected to a first level line, a second end of the first transistor is electrically connected to a signal line, a control end of the first transistor is electrically connected to a first end of the first switching device, a second end of the first switching device is electrically connected to the first level line, and a control end of the first switching device is electrically connected to the signal line.

Electro-static discharge circuit, array substrate, display panel and display apparatus

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Shanghai, China

Zhaokeng Cao