Boe Technology Group Co., Ltd.

Beijing Boe Display Technology Co., Ltd.

Beijing Boe Optoelectronics Technology Co., Ltd.

Zhaohui Hao

Ming Lei Zhang

Woong Sun Yoon

Lin Li

Yao Liu

Liang Sun

Liangliang Li

Jinchao Bai

Yongzhi Song

Zhenfei Cai

Pijian Jia

Seongyeol Yoo

Xu Wang

Cong Liu

Jianshe Xue

Seung Moo Rim

Yuchun Feng

Liping Luo

Zhixiao Yao

Guojing Ma

Haiyu Zhao

Chao Fan

Min Dong

Weidong Liu

Huzhao Shi

Chunze Zhang

Guoqi Mao

Huiyue Luo

Liquan Cui

Yuanyuan Hao

Lingqi Meng

Huaxing Zu

Yinzhong Zhang

Xiongxuan Yin

An array substrate and a fabrication method thereof are provided. The array substrate comprises a plurality of wiring regions (S-S') disposed in a non-display region, a plurality of signal lines () is provided in the wiring regions (S-S&#x2032;), at least part of the signal lines () within each of the wiring regions (S-S&#x2032;) are respectively formed by connecting conducting wires () located in different layers in series; and any two of the signal lines () within a same wiring region (S-S&#x2032;) have a resistance difference within a threshold range. The same signal line () is disposed in different layers, so that the signal line () is bent in a plane perpendicular to the array substrate, which achieves of the extension of a length of the signal line (), and thus increases the length and resistance of the signal line (), the resistance of which needs to be increased. At the same time, the width taken by the signal line () is not increased, so that the signal line () has a greater density in the wiring region (S-S&#x2032;), which achieves the reduction in the number of drivers and the fabrication costs, and meanwhile avoids a problem that it is not conducive to realize a narrow frame due to a large area of the non-display region, resulted from a large area taken by a single signal line ().

Array substrate and fabrication method thereof

The present disclosure provides a display substrate, including: a wiring mounting region. The wiring mounting region includes first wires and second wires, each of the first wires intersecting with one or more of the second wires, thereby defining one or more intersectional regions; and a semiconductor pattern between the first wire and the one or more second wires, the semiconductor pattern having at least one cross-sectional width covering at least a portion of at least one of the intersectional regions.

Display substrate, display device containing the same, and method for fabricating the same

The present disclosure provides a driving circuit for an array substrate, an array substrate, a display panel, and a display device. The driving circuit comprises a plurality of driving signal lines, which are insulated from each other and are used for driving a display region of the array substrate; and at least one driving circuit protection line insulated from the plurality of driving signal lines, wherein a voltage of the driving circuit protection line is smaller than that of each of the plurality of driving signal lines.

Driving circuit for array substrate, array substrate, display panel, and display device

An array substrate and a display device are provided. The array substrate includes a display region and a peripheral circuit region, wherein a first gate line, a first data line and a pixel region are arranged in the display region; the pixel region includes a first pixel electrode and a thin film transistor, and the thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode; the peripheral circuit region is provided with at least one test unit including: a second gate line; a second data line; a second testing pixel electrode; and a second testing thin film transistor. The second testing thin film transistor includes a second gate electrode, a second source electrode and a second drain electrode, wherein the second gate electrode, the second source electrode and the second drain electrode are provided with test ports exposed outside.

Array substrate and display device

Disclosed is an array substrate, a method for manufacturing the same, and a display device. The array substrate includes: a base substrate and a plurality of data lines disposed on the base substrate. The base substrate comprises a plurality of attaching areas in which the end of each data line attaches to the base substrate, and non-attaching areas between each two adjacent attaching areas, and a height layer is disposed between a passivation layer and the base substrate in the non-attaching area. By interposing a height layer between the passivation layer and the base substrate in the non-attaching area, the height difference between the passivation layer in the attaching area and the non-attaching area is decreased or disappeared, then the problem of fall-off of the passivation layer is solved, and the reliability of the product is increased.

Array substrate, method for manufacturing thereof, and display device

The array substrate according to the present disclosure may include within its fanout region a plurality of signal transmission lines for transmitting signals between a driver chip and a display region of the array substrate, and each signal transmission line may correspond to one data transmission channel. The array substrate may further include at least one impedance balancing line arranged corresponding to a signal transmission line in the plurality of signal transmission lines, wherein the impedance balancing line is electrically connected to the signal transmission line, so that a difference between impedances of different data transmission channels within the fanout region meets a first predetermined condition.

Array substrate, its manufacturing method, and display device

The present disclosure provides an array substrate, manufacturing method thereof and a display device. A method of manufacturing an array substrate includes: sequentially forming a common electrode line, a first insulating layer, a pixel electrode, and a second insulating layer, and forming a via that is in communication with the common electrode line. The method further comprises, after forming the via, forming a common electrode that covers the via through a patterning process, wherein the patterning process includes etching a portion of the via covered with the common electrode to form an isolated region. The isolated region includes a region at an inner side of a first edge of the via. The first edge is an edge of the via adjacent to or stacked with the pixel electrode. The via further includes a second edge that is neither adjacent to nor stacked with the pixel electrode.

Array substrate, manufacturing method thereof and display device

An array substrate is disclosed. The array substrate comprises a base substrate () and signal lines on the base substrate (). The signal lines comprises a plurality of conductive layers () in different layers, and the plurality of conductive layers () are provided with insulation layers () therebetween, and are connected in parallel through one or more vias (). Embodiments of the present disclosure further disclose a method for manufacturing the array substrate.

Array substrate and a method for manufacturing the same

A method of manufacturing an array substrate includes: forming a first functional layer comprising a plurality of array substrate areas and connection areas between adjacent array substrate areas; forming a plurality of conductive portions within each of the array substrate areas, the plurality of conductive portions extending from a corresponding one of the array substrate areas to a corresponding one of the connection areas and terminals of the plurality of conductive portions being in connection with capacitor lines within the corresponding one of the connection areas such that two capacitor lines between two adjacent array substrate areas face each other and are formed into a first capacitor element; forming a plurality of second functional layers on the first functional layer formed with the plurality of conductive portions and the capacitor lines, for forming a plurality of array substrates; and performing a cutting process at the connection areas between adjacent array substrates and removing the capacitor lines between the adjacent array substrates so as to form a plurality of separate array substrates. The present disclosure further provides an array substrate manufactured by the method.

Method of manufacturing array substrate and array substrate

An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate (); a common electrode () and a pixel electrode () sequentially formed on the substrate () and insulated from each other; a thin film transistor comprising a gate electrode (), an active layer (), a source electrode () and a drain electrode (), wherein the drain electrode () is electrically connected with the pixel electrode (); a common electrode line () disposed in a same layer as the gate electrode (); and an insulating layer () between the gate electrode () and the common electrode (), wherein the common electrode () is connected with the common electrode line () through a through hole in the insulating layer ().

Array substrate, method for manufacturing the same and display apparatus

An array substrate comprises a first substrate and a plurality of gate lines and a plurality of the data lines provided on the first substrate, the plurality of gate lines and the plurality of the data lines define a plurality of pixel units arranged into a matrix form. Each of the plurality of pixel units comprising: a first electrode having slits, comprising two or more regions where the slits have the different tilt degrees; a second electrode; and a thin film transistor switch, wherein the first electrode and the second electrode are used to form a horizontal electric field for driving liquid crystal molecules, the gate line and the thin film transistor switch are arranged between each two regions of the first electrode, and the thin film transistor switch is controlled by the gate line to operate each region of the first electrode.

Array substrate, liquid crystal panel and liquid crystal display

There is disclosed a method for manufacturing an Electro Static Discharge (ESD) device, an ESD device and a display panel, which are capable of addressing an issue that static-electric charges accumulated on the array substrate damage the unformed ESD device and improving a yield ratio of the array substrate. The method includes forming a TFT, a first lead wire, wherein the first lead wire or the second lead wire comprises at least two separate lead-wire segments; depositing a layer of passivation thin film, and forming via-holes for connecting the at least two separate lead-wire segments on the layer of passivation thin film; depositing a layer of transparent conductive film on the substrate on which the via-holes are formed, wherein the layer of transparent conductive film connects the lead-wire segments by the via-holes.

Method for manufacturing ESD device, ESD device and display panel

Embodiments of the present invention disclose an array substrate, a display device and a repair method of the array substrate. The array substrate comprises a display region; a peripheral region, in which a peripheral circuit including a plurality of leading wires is provided, and the peripheral region including: an insulation layer, provided above a layer in which the peripheral circuit is provided; and a leading wire repair layer, provided above the insulation layer, wherein the leading wire repair layer includes at least two common repair lines extended along an arrangement direction of the leading wires in the peripheral circuit, and a plurality of repair lines electrically connected the at least two common repair lines are provided between the two adjacent common repair lines.

Growing community of inventors

Beijing, China

Zhaohui Hao