Meta Platforms, Inc.

Zhao Wang

Yunqing Chen

Harikrishna Madadi Reddy

Gaurang Chaudhari

Baheerathan Anandharengan

Abdulkadir Utku Diril

Thomas Mark Ulrich

Junqiang Lan

Srikanth Alaparthi

Prahlad Rao Venkatapuram

Krishnakumar Narayanan Nair

Rakesh Komuravelli

A disclosed system may include a hardware distortion data pipeline that may include (1) a quantization module that generates a quantized data set, (2) an inverse quantization module that generates, from the quantized data set, an inverse quantized data set by executing an inverse quantization of the quantized data set, and (3) an inverse transformation module that generates an inversely transformed data set by executing an inverse transformation of the inverse quantized data set. The system may also include a hardware determination pipeline that determines a distortion metric based on the inversely transformed data set and the residual frame data set, and a hardware token rate pipeline that determines, based on the quantized data set, a token rate for an encoding of the residual frame data set via a video encoding pipeline. Various other methods, systems, and computer-readable media are also disclosed.

Hardware pipelines for rate-distortion optimization (RDO) that support multiple codecs

A device (e.g., integrated circuit chip) includes a first operand register, a second operand register, a multiplication unit, and a hardware logic component. The first operand register is configured to store a first operand value. The second operand register is configured to store a second operand value. The multiplication unit is configured to at least multiply the first operand value with the second operand value. The hardware logic component is configured to detect whether a zero value is provided and in response to a detection that the zero value is being provided: cause an update of at least the first operand register to be disabled, and cause a result of a multiplication of the first operand value with the second operand value to be a zero-value result.

Bypassing zero-value multiplications in a hardware multiplier

A video encoder comprises an application-specific integrated circuit (ASIC) video encoding unit configured to receive via an interface in a processing order, quantized transform coefficients for a transform unit of a frame of a video being encoded. The ASIC unit is configured to analyze at least a portion of the quantized transform coefficients in the processing order to identify one or more end-of-block candidate positions in the processing order. The ASIC unit is configured to translate the one or more end-of-block candidate positions for the at least a portion of the quantized transform coefficients to one or more scan order versions of the one or more end-of-block candidate positions. The ASIC unit is configured to determine a true end-of-block position for the quantized transform coefficients using the one or more scan order versions of the one or more end-of-block candidate positions.

End-of-block detection of quantized transform coefficient matrices in video encoding

A system for calculating token rates for video encoding includes a plurality of different probability lookup tables implemented in hardware, wherein each of the probability lookup tables specifically corresponds to a different prediction mode of a video codec. The system includes an application-specific integrated circuit compute unit. For each candidate prediction mode among the different prediction modes, the application-specific integrated circuit is configured to determine a rate distortion cost (RD Cost) for a video. The application-specific integrated circuit is configured to select one of the plurality of different probability lookup tables that corresponds to the candidate prediction mode and use the selected one of the plurality of different probability lookup tables to calculate a corresponding token rate for the candidate prediction mode. The application-specific integrated circuit is configured to encode the video using a selected one of the different prediction modes determined based on the determined rate distortion costs.

Hardware optimization of rate calculation in rate distortion optimization for video encoding

A quantized transform coefficient matrix is partitioned into a sequence of partition portions. The coefficients of the matrix are grouped into the sequence of partition portions based on a hardware implemented scan order. Each partition portion is processed in an order of the sequence in a first pass. For each partition portion, a group of coefficients in the partition portion is determined. For each partition portion, a first data rate estimation for the quantized transform coefficient matrix is updated based on at least some coefficients of the group of coefficients in the partition portion and a maximum end-of-block. For each partition portion, an end-of-block estimation of the quantized transform coefficient matrix is updated based on at least some coefficients of the group of coefficients in the partition portion. A first resulting data rate estimation and a true end-of-block of the quantized transform coefficient matrix are determined after the first pass.

Architecture for rate estimation in video coding

A floating-point number in a first format representation is received. Based on an identification of a floating-point format type of the floating-point number, different components of the first format representation are identified. The different components of the first format representation are placed in corresponding components of a second format representation of the floating-point number, wherein a total number of bits of the second format representation is larger than a total number of bits of the first format representation. At least one of the components of the second format representation is padded with one or more zero bits. The floating-point number in the second format representation is stored in a register. A multiplication using the second format representation of the floating-point number is performed.

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Newark, CA, United States of America

Zhao Wang