Cirrus Logic Inc.

Zhao Kan

Prabir C Maulik

Chadha S Mandeep

A scalable FIR filter architecture that requires fewer computations, less storage registers, and is capable of parallel processing, is presented. The scalable filter architecture reduces the number of computations (e.g., multiplication) by utilizing the inherent symmetry and reduces the number of storage elements required by utilizing what is known as the transpose-form (as compared to direct-form) filter architecture. The filter architecture is scalable to accommodate different complexity levels. In accordance to the present invention, a filter can be scaled up/down by adding/subtracting a processing block to/from the existing structure. Because these processing blocks can process signals independently and simultaneously, the filter architecture in accordance to the present invention allows for parallel and distributive processing thereby meeting the required performance requirements.

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Austin, TX, United States of America

Zhao Kan