Yangtze Memory Technologies Co., Ltd.

Zhao Hui Tang

Li Hong Xiao

Yu Ting Zhou

Qian Tao

Zhaosong Li

Sizhe Li

Zhenyu Lu

Yushi Hu

Jun Chen

Jin Wen Dong

Yue Qiang Pu

Sha Sha Liu

EnBo Wang

Jian Xu

Zongliang Huo

Jun Liu

Xiaowang Dai

Mei Lan Guo

Qianbing Xu

Qinxiang Wei

Jian Hua Sun

ZhiWu Tang

Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Multiple-stack three-dimensional memory device and fabrication method thereof

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Memory device and forming method thereof

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a first dielectric layer, and a second dielectric layer. The memory stack includes interleaved conductor layers and dielectric layers above the substrate. The memory stack includes a staircase structure at one edge of the memory stack. The channel structure extends vertically through the memory stack. The first dielectric layer is above the memory stack. A part of the first dielectric layer right above the staircase structure has a dished bottom surface. The second dielectric layer is on the part of the first dielectric layer right above the staircase structure and has a nominally flat top surface.

Methods for forming three-dimensional memory device without conductor residual caused by dishing

Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Through array contact (TAC) for three-dimensional memory devices

Disclosed is a method for forming a staircase structure of 3D memory devices, comprising (i) forming a stack of layers on a substrate; (ii) removing a portion of the stack to form a lower region and a upper region; (iii) forming a mask to cover the lower region and the upper region of the stack; (iv) forming a first opening in the mask to expose a first portion of the stack in the lower region and a second opening in the mask to expose a second portion of the stack in the upper region; (v) forming a photoresist layer to cover the stack and the mask; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases in the first opening and the second opening; (vii) removing the photoresist layer and the mask; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Method for forming staircase structure of three-dimensional memory device

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces.

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers is formed above a substrate. A dummy channel structure extending vertically through the dielectric stack is formed. An elevating dielectric layer is formed on a dummy dielectric layer. A slit opening extending vertically through the elevating dielectric layer, dummy dielectric layer, and dielectric stack is formed. A memory stack including interleaved conductor layers and the dielectric layers is formed above the substrate by gate replacement. A source contact is formed in the slit opening by depositing a source conductor layer on the elevating dielectric layer and in the slit opening. The source conductor layer on the elevating dielectric layer and at least a part of the elevating dielectric layer are removed.

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Embodiments of a method for forming a staircase structure of 3D memory devices are disclosed. The method comprises (i) forming an alternating layer stack including multiple layers disposed on a substrate in a vertical direction; (ii) removing a portion of the alternating layer stack to form multiple step-platforms in a staircase region of the alternating layer stack; (iii) forming a hard mask layer to cover top surfaces of the step-platforms; (iv) forming multiple openings in the hard mask layer to expose a portion of each of the step-platforms; (v) forming a photoresist layer to cover the top surfaces of the step-platforms and the hard mask layer; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases on each of the step-platforms; (vii) removing the photoresist layer and the hard mask layer; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Growing community of inventors

Hubei, China

Zhao Hui Tang