Taiwan Semiconductor Manufacturing Comp. Ltd.

Zhao-Cheng Chen

Yu-Lien Huang

Ming-Huan Tsai

Clement Hsingjen Wann

Chi-Wen Liu

Chung-Ju Lee

Chih Wei Lu

Hsiang-Ku Shen

Chien-Hua Huang

Chun-Hsiang Fan

Tsu-Hsiu Perng

A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Semiconductor device having modified profile metal gate

A semiconductor device includes a first conductive structure directly over an isolation structure; a second conductive structure directly over an active region; a first dielectric layer over the first and second conductive structures; a second dielectric layer over the first dielectric layer, wherein the first and second dielectric layers include different materials; a first conductive feature contacting the first conductive structure through at least the first and second dielectric layers; and a second conductive feature contacting the second conductive structure through at least the first and second dielectric layers, wherein the first and second conductive features include a same metal.

Method and structure for semiconductor mid-end-of-year (MEOL) process

A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.

Method of fabricating a semiconductor device having modified profile metal gate

A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.

Method and structure for semiconductor mid-end-of-line (MEOL) process

A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.

Semiconductor device and fabrication method thereof

A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.

A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.

A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.

In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers.

A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure. The first dummy gate structure is removed after forming the protective layer, thereby providing a first trench. A capping layer (e.g., silicon) is formed in the first trench. A metal gate structure may be formed on the capping layer. The protective layer may protect the second dummy gate structure during the removal of the first dummy gate structure.

Growing community of inventors

Taipei, Taiwan

Zhao-Cheng Chen