Cisco Technology, Inc.

Cadence Design Systems, Inc.

Public Wireless, Inc.

Zhanhe Shi

Qingming Ma

Saravanan Agasaveeran

Steven Howard Berl

Pinchas Herman

Duc The Dang

David Abada

Ty Doan

Pradeep Kumar Kathail

Quang Nguyen

Claude Alan Cartee

Vu T Nguyen

Nart Bajj

Akash Sharma

Brett Moser

Raju Joshi

A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

Synchronized reset for a circuit emulator

A reconfigurable switching apparatus may include a plurality of communications transceivers operable to connect to a plurality of programmable integrated circuits. The reconfigurable switching apparatus may further include a plurality of crosspoint switches operably coupled to the plurality of communications transceivers. The reconfigurable switching apparatus may further include a processing circuitry operably coupled to the plurality of crosspoint switches and operable to program the plurality of crosspoint switches to route a plurality of interconnection paths between the plurality of communications transceivers.

Reconfigurable switch for a computing system

A method includes programming an FPGA based controller of a master blade with a power scheme. The master blade receives a first power management signal from the master blade and slave blades. The master blade transmits a second power management signal to itself and to the slave blades responsive to the first power management signal. The master blade receives a third power management signal from itself and the slave blades. The power scheme controls an order and delay in which the second power management signal is transmitted to the first master blade and the slave blades. The power scheme controls an order and delay in which the third power management signal is received from the master blade and the slave blades. The system can be expanded by connecting the master blades to a grand master blade and multiple grand master blades to a great grand master blade.

Multi-modal power control

A multi-modal multi-modulation base station such as a small cell eNB is disclosed. The small cell eNB includes multiple radio devices that can be configured to communicate with user devices using different protocols and different frequencies. The small cell eNB also includes a sniffer module to detecting signal from other base stations. The small cell eNB include functions to automate deployment in a self-organizing network, such as network monitoring, neighbor peer discovery, processing of neighbor peer reports, automated transmit-power adaptation, processing of user equipment reports, physical cell identity selection, automatic neighbor relation, handover configuration, private access connections, load balancing, RACH preamble power control, RACH preamble set selection, RACH preamble splitting, PRACH configuration, and mobility robustness.

Systems and methods for deployment operations for small cells in self-organizing networks

Controlling congestion in a networking device having a plurality of input interface queues comprises estimating, in each of one or more sampling states, a data arrival rate for each of the plurality of input interface queues with respect to incoming data packets received on corresponding input interfaces, obtaining a set of estimated arrival rates for the plurality of the input interface queues, determining, for each polling state associated with a respective sampling state, the sequence in which the plurality of input interface queues should be polled using the set of estimated data arrival rates of the plurality of input interface queues, and polling the plurality of interface queues in accordance with the determined sequence. The sequence indicates when, during a single polling cycle, each of the input interface queues should be polled in relation to every other of the input interface queues.

Apparatus and method for rate-based polling of input interface queues in networking devices

A method for dynamically building a packet processing chain includes providing a plurality of packet processing elements. For each element of a first subset of elements operations indications are provided. For each element of a second subset of elements, expectations indications are provided. Finally, the chain is built by combining elements to form the chain according to a configuration requirement. Elements are selected such that an element's indicated expectations are satisfied by the time it executes, as indicated by the operations indications of the previous chain element.

Dynamically building encapsulation and decapsulation chains at run time

The congestion control in a networking device having a plurality of input interface queues includes (a) estimating the data arrival rate on each of the plurality of input interface queues, and (b) determining, for each polling round, the sequence in which the plurality of input interface queues should be polled and the quantity of data to be processed from each of the plurality of input interface queues each time the input interface queue is polled, using the estimated data arrival rate on each of the plurality of input interface queues.

A two-phase packet processing technique is provided for routing traffic in a packet-switched, integrated services network which supports a plurality of different service classes. During Phase I, packets are retrieved from the router input interface and classified in order to identify the associated priority level of each packet and/or to determine whether a particular packet is delay-sensitive. If it is determined that a particular packet is delay-sensitive, the packet is immediately and fully processed. If, however, it is determined that the packet is not delay-sensitive, full processing of the packet is deferred and the packet is stored in an intermediate data structure. During Phase II, packets stored within the intermediate data structure are retrieved and fully processes. The technique of the present invention significantly reduces packet processing latency, particularly with respect to high priority or delay-sensitive packets. It is easily implemented in conventional routing systems, imposes little computational overhead, and consumes only a limited amount of memory resources within such systems.

Packet prioritization processing technique for routing traffic in a packet-switched computer network

The invention provides unique mechanisms and techniques for a computing device to perform various tasks in a multi-tasking or time sliced environment. A general task scheduling algorithm can select various time slices or priorities for task performance. However, in a dedicated device such as a data communications device, a primary task such as a data transfer task may be so heavily favored by the general task scheduling algorithm, such as in heavy network traffic conditions, that other tasks may be starved of processor time. As such, the system of the invention allows the primary task, to track a first time period Y, and upon expiration of this time period Y, to generate a yield signal to a yielding scheduler. The yielding scheduler can then disable performance of the primary task(s) and track a second time period X during which other tasks may be performed. At the expiration of the second time period X, the primary task(s) which were disabled upon the occurrence of the yield signal are then re-enabled for performance and the yielding scheduler selects a task for performance. Generally, the primary task will again be selected over, for example, lower priority tasks. However, the lower priority tasks will have had a chance to perform irrespective of the general task scheduling algorithm since the primary task(s), which may be heavily scheduled, can control the yielding of processor time. By selecting various values for the time periods X and Y, different aspects of device operation can be controlled to provide a balanced system that can greatly avoid task starvation while also meeting the response time requirements of the primary task and the other lower priority task(s). Since the tasks themselves are given control over the ability to yield time to other tasks, flexibility is provided by the system of the invention.

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San Jose, CA, United States of America

Zhanhe Shi