Beijing Boe Optoelectronics Technology Co., Ltd.

Boe Technology Group Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Beijing Boe Display Technology Co., Ltd.

Wuhan Boe Optoelectronics Technology Co., Ltd.

Zhangtao Wang

Haijun Qiu

Tae Yup Min

Xibin Shao

Haipeng Yang

Ke Dai

Xu Chen

Seung Moo Rim

Peng Hui Jiang

Lei Guo

Yanping Liao

Rui Ma

Hongtao Lin

Maoxiu Zhou

Yong Jun Yoon

Zhihua Sun

Tong Yang

Yingmeng Miao

Bin Feng

Jiarong Liu

Yuntian Zhang

Xianjie Shao

Yuanhui Guo

Yongjun Yoon

Yujie Gao

Yongcan Wang

Li Yin

Zhixiao Yao

Bingbing Yan

Yusheng Xi

Weihua Jia

Yanchun Lu

Shuishui Zhang

Min Zhong

A display substrate has a display area and an encapsulation area around the display area. The display substrate includes a substrate and a spacer layer. The spacer layer is located on a side of the substrate, and includes a plurality of first columnar spacers located in the encapsulation area and distributed at intervals around the display area, and bottom ends of the plurality of first columnar spacers are fixedly disposed on the substrate. Ends of the plurality of first columnar spacers proximate to the substrate are the bottom ends thereof, and ends of the plurality of first columnar spacers away from the substrate are top ends thereof.

Display substrate and manufacturing method therefor, and display device

An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Array substrate and display panel

The present application discloses a shift-register circuit including a shift-register unit and a shutdown-discharge sub-circuit. The shift-register unit is coupled to a clock port, a first reference voltage port, a second reference voltage port, and an output port and configured to set a voltage level at a pull-up node to control a clock signal from the clock port being outputted to the output port to drive a display panel during a display period. The shutdown discharge sub-circuit is configured to at least simultaneously receive at least one shutdown signal at a first voltage level from a shutdown-discharge control port and a second signal at the first voltage level from the second reference voltage port to start a shutdown period to discharge at least one of the pull-up node and the output port.

Shift-register circuit, a driving method thereof, and related display apparatus

The present disclosure provides a liquid crystal display panel and a display device, including: a liquid crystal panel, a light control panel, and a polarizer located on a surface of the liquid crystal panel away from the light control panel that are stacked, in which the polarizer includes a pressure-sensitive adhesive layer in contact with the liquid crystal panel, and the pressure-sensitive adhesive layer has a light adjustment structure configured to adjust a propagation path of light emitted from the liquid crystal panel by means of refraction or total reflection. The liquid crystal display panel provided by the present disclosure can improve or even eliminate the rainbow pattern phenomenon, and improve the display quality of the liquid crystal display panel.

Liquid crystal display panel and display device

The present application discloses a shift-register circuit including a shift-register unit and a shutdown-discharge sub-circuit. The shift-register unit is coupled to a clock port, a first reference voltage port, a second reference voltage port, and an output port and configured to set a voltage level at a pull-up node to control a clock signal from the clock port being outputted to the output port to drive a display panel during a display period. The shutdown discharge sub-circuit is configured to at least simultaneously receive a shutdown signal at a first voltage level from a shutdown-discharge control port and a second signal at the first voltage level from the second reference voltage port to start a shutdown period to discharge at least one of the pull-up node and the output port. The shutdown signal has a signal length longer than a signal length of the second signal.

Embodiments of the disclosure provide an array substrate, a manufacturing method for an array substrate, a display panel, and a display apparatus. The array substrate according to one embodiment including a gate line extending in a first direction, a data line extending in a second direction different from the first direction, a first common electrode line extending in the first direction, a second common electrode line extending in the second direction, and common electrodes in which the common electrodes at both sides of and adjacent to the second common electrode line are electrically connected to the second common electrode line.

Array substrate, manufacturing method thereof, display panel and display apparatus

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes a plurality of mutually parallel signal lines, an insulating layer located on a layer in which the plurality of signal lines is located and at least one first conductive structure located on the insulating layer. The insulating layer includes at least two first through holes corresponding to the first conductive structure, and the first conductive structure is electrically connected with the signal lines through the at least two first through holes.

Array substrate and manufacturing method thereof, and display device

An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes a base substrate, a plurality of pixel units arranged in a matrix and a plurality of common electrode lines extending along the column direction on the base substrate. There are two scanning signal lines between two adjacent rows of pixel units, and pixel units in a (2N+1)-th column and a (2N+2)-th column are taken as one pixel unit group, N being selected from integers greater than or equal to zero. The respective common electrode lines are located between two adjacent pixel unit groups.

Array substrate and manufacturing method thereof, display panel and display device

An array substrate, a method of manufacturing the same and a liquid crystal display panel are disclosed. In the array substrate, a connection part for connecting two adjacent pixel electrodes is configured to enclose the spacer from three sides and a corresponding thin film transistor is arranged to enclose the spacer from a side other than the three sides. A distance between an upper surface of the connection part and an upper surface of the base substrate is larger than a distance between a lower surface of the spacer and the upper surface of the base substrate. With this configuration, the spacer is limited within a position limiting structure formed by the connection part and the thin film transistor.

Array substrate, method of manufacturing the same, and liquid crystal display panel

An array substrate comprises a TFT, a data line, a gate line and a passivation layer covering the TFT, the data line and the gate line. The array substrate further includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is disposed on the passivation layer and above the TFT, and the second conductive structure is disposed on the passivation layer and above the data line and/or gate line. A method for manufacturing the array substrate and a display device having such an array substrate are also provided.

Array substrate, method for manufacturing the same, and display device

A pixel unit comprises a pixel electrode, a data line and a TFT, and further comprises: a backup TFT, a source electrode of which is isolated from the data line, and a drain electrode of which is isolated from the pixel electrode; a first repair line, one end of the first repair line and the source electrode of the backup TFT being isolated from each other and there being an overlapping region therebetween, and the other end of the first repair line and the data line or a source electrode of the TFT being isolated from each other and there being an overlapping region therebetween; and a second repair line.

Pixel unit, array substrate, method for manufacturing array substrate, method for repairing array substrate, and display device

Embodiments of the invention provide an array substrate comprising a plurality of pixel units, each of the pixel units including a first display electrode, a second display electrode and an insulating portion, wherein, the insulating portion comprises a plurality of first via holes; the first display electrode is disposed at a surface of the insulating portion, and the second display electrode is disposed at bottom surfaces of the first via holes. Embodiments of the invention further provide a method for manufacturing the array substrate.

Array substrate and manufacturing method thereof

A TFT array substrate and a manufacturing method thereof, where the TFT array substrate includes a substrate; a gate line and a gate electrode integrated therewith, which are covered by a gate insulating layer, a semiconductor layer, and a ohmic contact layer sequentially. An insulating layer is formed on the resulting substrate and on both sides of the gate line and the gate electrode, the gate insulating layer, the semiconductor layer, and the ohmic contact layer. A trench is then formed in the ohmic contact layer to divide the ohmic contact layer over the semiconductor layer. A data line and first and second source/drain electrodes are then formed on the insulating layer and the ohmic contact layer.

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Beijing, China

Zhangtao Wang