Marvell International Limited

Agere Systems Inc.

University of California

Zhan Yu

Weishi Feng

Runsheng He

Kameran Azadet

Meng-Lin Yu

Liang Zhang

Alan Neil Willson, Jr

Larry S Wasserman

Circuits, architectures, methods, algorithms, software, and systems for increasing reliability of data communications using time diversity coding are disclosed. An association circuit is configured to associate a first reliability factor with a first copy of the communicated data and a second reliability factor with a second copy of the communicated data, wherein the first reliability factor is different from the second reliability factor and has a value that is a predetermined function of a known characteristic of the data communications channel at a time that the communicated data passed through the channel. A decoder is configured to recover a reliable value for the communicated data from the first copy, second copy, first reliability factor, and second reliability factor.

Circuits, architectures, methods, algorithms, software, and systems for improving the reliability of data communications having time-dependent fluctuations

Methods, software, receivers and systems for communicating information over a cyclostationary channel. The method generally includes interleaving sections of a control sequence with bits of the information. The software and receivers are generally configured to implement one or more aspects of the methods disclosed herein, and the systems generally include those that embody the inventive receivers disclosed herein. The present invention is particularly useful in powerline channels, where certain parameters (such as noise) have time-dependent or periodic variations in value. By distributing the control sequence, the incidence of carrier recovery is reduced, the likelihood of successful packet or frame transmissions is increased, and data may be more reliably communicated.

Methods, algorithms, software, circuits, architectures, and systems for improved communications over cyclostationary channels

A data encoding system includes an interleaving module, a generating module, and an insertion module. The interleaving module is configured to receive a data stream. The data stream includes a plurality of data blocks. The interleaving module is configured to, for each data block of a selected subset of the plurality of data blocks, swap positions of a pair of adjacent bits of the data block. The generating module is configured to (i) receive the data stream and (ii) for each of the plurality of data blocks, generate at least one corresponding error checking bit. The insertion module is configured to (i) receive the plurality of data blocks as modified by the interleaving module and (ii) generate an output data stream by inserting the at least one corresponding error checking bit into each one of the plurality of data blocks received from the interleaving module.

Universal parity encoder

A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

Universal parity decoder

A data dependent scrambler for a communications channel that receives a user data sequence including N symbols and host cyclic redundancy check (CRC) bits comprises a data buffer that receives the user data sequence and the host CRCbits. A seed finder generates a scrambling seed that is dependent upon the symbols in the user data sequence. A first scrambler receives the user data sequence from the data buffer and the scrambling seed from the seed finder and generates the scrambled user data sequence. A second scrambler generates a difference sequence that is based on the user data sequence and the scrambled user data sequence.

Methods of supporting host CRC in data storage systems without RLL coding

A seed generator for a scrambler comprises a seed set identifier that identifies a seed set based on received user data symbols, which include a plurality of M-bit symbols. A seed selector selects a scrambling seed for the scrambler from the seed set based on Hamming distances between at least two of the M-bit symbols in the seed set.

Method and apparatus for generating a seed set in a data dependent seed selector

An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

Low power vector summation apparatus

A Reed-Solomon decoder includes an inversionless Berlekamp-Massey algorithm (iBMA) circuit with a pipelined feedback loop. A first polynomial generator generates error locator polynomial values. A discrepancy generator generates discrepancy values based on the error locator polynomial values and the scratch polynomial values. Arithmetic units are used to generate the discrepancy values are also used to generate the error locator polynomial to reduce circuit area. A first delay circuit delays the discrepancy values. A feedback loop feeds back the delayed discrepancy values to the error locator polynomial generator. An error location finder circuit communicates with the iBMA circuit and identifies error locations. An error value computation circuit communicates with at least one of the error location finder circuit and the iBMA circuit and generates error values.

Efficient high-speed Reed-Solomon decoder

A communications channel comprises a seed selector that selectively removes X M-bit symbols of user data from a seed set comprising Y M-bit symbols and that selects a scrambling seed from Y-X symbols remaining in the seed set, where X, Y and M are integers greater than one. A Hamming weight coding device that determines a Hamming weight of symbols of scrambled user data that are generated based on the user data and the selected scrambling seed and that selectively codes the symbols depending upon the determined Hamming weight.

Methods and apparatus for improving minimum hamming weights of a sequence

A system for detecting errors in received input data includes a first error detection circuit. The first error detection circuit is configured to receive the input data. The input data includes at least one of data and data with errors. The first error detection circuit is configured to generate a first error detection sequence in a first order. The system includes a second error detection circuit. The second error detection circuit is configured to receive the first error detection sequence and an error sequence. The error sequence is received in a second order that is different from the first order when there is data with errors. The second error detection circuit is configured to generate a second error detection sequence that indicates whether the error sequence is generated correctly.

Method and apparatus for checking read errors with two cyclic redundancy check stages

An error correcting Reed-Solomon decoder includes an error locator polynomial generator that generates an error locator polynomial and a scratch polynomial based on an inversionless Berlekamp-Massey algorithm (iBMA). An error location finder communicates with the error locator polynomial generator and generates error locations. An error values finder communicates with the error locator polynomial generator and generates error values directly from the error locator polynomial and the scratch polynomial.

Error evaluator for inversionless Berlekamp-Massey algorithm in Reed-Solomon decoders

A communications channel that receives a user data sequence including N symbols and that supports host CRC includes a host bus interface (HBI) that generates cyclic redundancy check (CRC) bits based on the user data sequence. A data dependent scrambler (DDS) receives the user data sequence and the CRCbits and generates a scrambling seed. The DDS generates a scrambled user data sequence that is based on the user data sequence and the scrambling seed and generates a difference sequence.

An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of 'transition probabilities' is encountered.

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Sunnyvale, CA, United States of America

Zhan Yu