Broadcom Corporation

Micron Technology Incorporated

Zeynep M Toros

Esin Terzioglu

Gil I Winograd

Ali Anvar

Ahmad O Siksek

Sandor L Barna

Igor Subbotin

Sami Issa

Michael Kaplinsky

Kwang-Bo Cho

Cyrus Afghahi

Aspects of the invention for testing and debugging an embedded device under test may include the step of loading an instruction into a parameterized shift register of a BIST module coupled to each one of a plurality of embedded memory modules comprising the embedded device under test. An identity of the loaded instruction may be determined subsequent to loading the instruction into the parameterized shift register. A plurality of test signals may be generated which correspond to the determined identity of the loaded instruction. In this regard, each of the generated plurality of test signals may control the execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules that make up the embedded device under test.

Software programmable verification tool having a single built-in self-test (BIST) module for testing and debugging multiple memory modules in a device under test (DUT)

Image sensor with a successive approximation A/D converter that automatically compensates for black level and provides a signal indicative of the difference between the reset level and the signal level. Black level for each of a plurality of color pixels may be obtained. This may be obtained from, for example, an image sensor with intentionally darkened pixels. Levels from these pixels are sampled, and an average of these pixels is used to form a black level for similarly-colored pixels. That black level is stored, and used to drive a D/A converter. Another D/A converter forms the actual conversion, and is compared to a reference. The reference is selected such that the output signal is automatically compensated for black level, and also corresponds to the difference between signal and reset.

Imaging apparatus providing black level compensation of a successive approximation A/D converter

In a digital memory system, systems and methods that control a logical value and an integrity of data represented by charge are provided. In one embodiment, a bit line is coupled to the cell. A voltage generator is arranged to generate a plurality of cell operating voltages varying in response to a voltage control signal. A controller generates a control signal, stores a predetermined one of logical values in a cell by generating a series of operating voltages, transmits the series of operating voltages, and determines whether the predetermined one of the logical values has been stored in the cell in response to a voltage on the bit line. The controller includes a charge integrity estimating module and determines whether the predetermined one of the logical values has been stored in the cell by initiating the operation of the charge integrity estimating module.

System and method for controlling logical value and integrity of data in memory systems

A digital memory system () includes a memory cell (), a bit line (), a voltage generator () a controller () and a charge integrity estimating module (). A series of successively larger operating voltages are transmitted to the cell from the voltage generator. The controller determines whether a predetermined value has been stored in the cell. The charge integrity estimating module detects the quantity of charge in the memory cell, for example, by using a sense amplifier ().

Non-volatile memory apparatus and method capable of controlling the quantity of charge stored in memory cells

A random access memory cell ( ) includes a first conductor line ( ) and a second conductor line ( ). A native device ( ) is arranged to store charge. A high voltage threshold transistor ( ) couples the native device to the first and second conductors.

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Irvine, CA, United States of America

Zeynep M Toros