Applied Materials, Inc.

Zeqiong Zhao

Ganesh Balasubramanian

Deenesh Padhi

Zhijun Jiang

Allison Yau

Akhil Singhal

Sang-Jin Kim

Shashank Sharma

Abhilash J Mayur

Jianhua Zhou

Suhail Anwar

Zheng John Ye

Norman L Tam

Andrew C Lam

Matthew Spuller

Xinming Zhang

Yoshitake Nakajima

Hshiang An

Fu-ting Chang

Embodiments of the present disclosure generally relate to methods and apparatus for measuring and controlling local impedances at a substrate support in a plasma processing chamber during processing of a substrate. A substrate support includes a plurality of substrate support pins wherein the radio frequency voltage, current and phase of each of the plurality of substrate support pins are measured and impedances of the support pins are adjusted in real time. Each of the substrate support pins is coupled to an associated adjustable impedance circuit that may be remotely controlled. In one embodiment a variable capacitor is used to adjust the impedance of the impedance circuit coupled to the associated substrate support pin and may be remotely adjusted with a stepper motor. In another embodiment a microcontroller may control the impedance adjustments for all of the plurality of substrate support pins and may be used to track these impedances with each other and with a bulk impedance of the plasma processing chamber.

Impedance control of local areas of a substrate during plasma deposition thereon in a large PECVD chamber

Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

Systems and methods of seasoning electrostatic chucks with dielectric seasoning films

Exemplary deposition methods may include delivering a silicon-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the inert gas. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The processing region may be maintained free of helium delivery during the deposition method.

Helium-free silicon formation

Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.

Profile shaping for control gate recesses

Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 &#x212b;.

The present disclosure provides systems and methods for processing channel structures of substrates that include positioning the substrate in a first processing chamber having a first processing volume being in fluid communication with a plasma source. The substrate can include a channel structure with high aspect ratio features having aspect ratios greater than about 20:1. The method can also include forming an oxide cap layer over a silicon-containing layer of the channel structure and exposing the oxide cap layer to a hydrogen-or-deuterium radical to nucleate the silicon-containing layer of the channel structures of the substrate. Forming the oxide cap layer and exposing the channel structure with the hydrogen radical occurs in the first processing chamber to form a nucleated substrate. The method can also include positioning the nucleated substrate in a second processing chamber with a second processing volume and heating the nucleated substrate in the second processing chamber.

System and method for radical and thermal processing of substrates

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Santa Clara, CA, United States of America

Zeqiong Zhao