Western Digital Technologies, Inc.

Sandisk Information Technology (shanghai) Co., Ltd.

Zengyu Zhou

Chin-Tien Chiu

Hope Chiu

Rui Yuan

Cong Zhang

Jiandi Du

Fen Yu

Paul Qu

Shixing Zhu

Yi Su

Kevin Du

Jun Zhu

Yazhou Zhang

Yangming Liu

Rui Guo

Chin Tien Chiu

Binbin Zheng

Zhongli Ji

Fuqiang Xiao

Vincent Jiang

Emma Wang

Linda Huang

Shaopeng Dong

Juan Zhou

Joyce Chen

Haijun Wu

Lynn Lin

Alex Zhang

A memory device includes a substrate, a controller die, a flip chip die, first and second silicon dies, and bond wires. The controller and flip chip dies are attached to the substrate using connection balls and in electrical communication with each other. The first and second silicon dies include respective first and second contact pad surfaces. The bond wires electrically connect the contact pad surfaces to the substrate so the first and second silicon dies communicate with the controller die. The flip chip die and first and second silicon dies are NAND dies, the flip chip die is configured as SLC memory, and the silicon dies are configured as one of MLC memory, TLC memory, or QLC memory.

Packaged memory device with flip chip and wire bond dies

A packaged semiconductor includes a substrate and a first component disposed on the substrate. The package includes an underfill that is dispensed under and around the first component. The package also includes a second component disposed on the substrate adjacent to the first component that provides a border to the underfill.

Reducing keep-out-zone area for a semiconductor device

A surface mount device having features on contacts to prevent the surface mount device from tombstoning. The feature may be channel defined by the contact that helps balance a torque/force applied on each side of the surface mount device during a reflow soldering process. The feature may also be a solder mask that helps balance a torque/force applied on each side of the surface mount device during a reflow soldering process.

Tombstone prevention for a surface mount device

A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.

Substrate component layout and bonding method for increased package capacity

A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.

Semiconductor device including conductive bumps to improve EMI/RFI shielding

A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.

Semiconductor device including high speed heterogeneous integrated controller and cache

A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.

Semiconductor device including vertically integrated groups of semiconductor packages

A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. The wire bonds to the top die may be provided in the spacing. An RDL pad is affixed to the surface of the mold compound. Columns of bumps may be formed on the die bond pads of the top die in the die stack to electrically couple the RDL pad to the die stack across the spacing.

Fan out semiconductor device including a plurality of semiconductor die

Growing community of inventors

Shanghai, China

Zengyu Zhou