Advanced Micro Devices Corporation

ZengRong Huang

Ling-Ling Wang

HaiKun Dong

Jie Gao

MinHua Wu

Wei Shao

XiaoJing Ma

Yuan Du

Shenyuan Chen

LingFei Shi

RuiHong Liu

Qian Zong

Apparatuses, systems and methods for performing efficient power management for a processing unit. A processing unit includes two partitions, each assigned to a respective power domain with operating parameters, and each with a respective direct memory access (DMA) engine. If a controller determines a task type of a received task indicates the task is to be processed by components of the second partition, then the controller assigns the task to the second partition and maintains the operational parameters of the first power domain for the components of the first partition or selects lower performance operational parameters of the first power domain. The processing unit accesses data stored in memory using a DMA engine and operational parameters of the second partition. Additionally, the second partition processes the task using the operational parameters of the second power domain.

Processor power management utilizing dedicated DMA engines

Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.

Centralized interrupt handling for chiplet processing units

Growing community of inventors

Shanghai, China

ZengRong Huang